Dual-Domain Memory Cell for Cryogenic Low Latency

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Solution Overview

Problem

Integrated-circuit memory technologies face challenges in reducing data output latency and increasing drive current, particularly in voltage-scaled cryogenic applications, where conventional single-domain memory cells exhibit long settling delays due to high-capacitance signal lines and increased transistor gate delay.

Innovation Solution

The implementation of dual-domain integrated-circuit memory with small-swing control signals and large-swing data storage elements, where control signals swing between two voltage domains, enabling cross-domain signals to generate high drive currents and reduce latency by super-driving output transistors beyond the transistor threshold voltage, allowing for rapid charging and discharging of bitlines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional single-domain memory cells are used, then device simplicity is maintained, but data output latency increases due to long settling delays

Engineering Contradiction:

Improvedata output latencyVSAvoidmemory cell structure

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The memory system is divided into two separate voltage domains (first voltage domain and second voltage domain) with different voltage levels. The memory cell operates with storage nodes in one domain while using cross-domain transistors to interface with the other domain, enabling faster signal transitions without complicating the basic memory cell structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Cross-domain transistors act as intermediary elements between the first voltage domain and the second voltage domain. These transistors enable rapid charging and discharging of bitlines by providing a low-impedance path for current flow during read operations, thereby reducing settling delays without requiring fundamental changes to the memory cell architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Use of energy by moving object

If voltage-scaled cryogenic applications are used, then power consumption is reduced, but transistor gate delay increases

Engineering Contradiction:

Improvepower consumptionVSAvoidtransistor gate delay

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The invention changes the voltage domain parameter by introducing a second voltage domain with higher voltage levels compared to the first voltage domain. This parameter change enables faster transistor switching in the cross-domain transistors, compensating for the increased gate delay inherent in voltage-scaled cryogenic applications, while still maintaining low power consumption through the use of cryogenic operating temperatures.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10726901B1Dual-domain memory

Publication Date: 2020.07.28 RAMBUS INC

AI summary

A memory cell within an integrated-circuit memory component receives a first control signal that transitions between supply voltage levels of a first voltage domain and a second control signal that transitions between supply voltage levels of a second voltage domain different from the first voltage domain. In response to the transitions of the first and second control signal, output-enable circuitry within the memory cell transitions an output-enable signal between one of the supply voltage levels of the first voltage domain and one of the supply voltage levels of the second voltage domain to enable output signal generation on an output signal line coupled to the memory cell.