CMOS DRAM Cell with Dual Transistors and Single-Ended Read Path
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Single transistor DRAM cells experience high stress during activation and inactivation due to significant voltage swings, leading to performance degradation, while CMOS DRAM cells with dual transistors face issues with doubled capacitance on the bit line, reducing charge transfer ratio and causing retention degradation.
Innovation Solution
A CMOS DRAM cell configuration using a pair of bit lines, where an n-type field-effect transistor (NFET) and a p-type field-effect transistor (PFET) are used to access a storage capacitor, allowing only one bit line for reading and both for writing, with a sense amplifier that differentiates between logical '0' and '1' values for write-back operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single transistor DRAM cell uses large voltage swings (>2.0V) for activation and inactivation, then the charge transfer ratio is improved (70% charge transfer), but the transistor experiences excessive stress leading to performance degradation
Solution Approach 1:
The patent divides the single transistor into two separate transistors (NFET and PFET), each controlled by its own word line. This segmentation allows each transistor to operate with smaller, less stressful voltage swings while collectively achieving the required charge transfer functionality through complementary operation.
Solution Approach 2:
The patent changes the voltage swing parameters from large swings (>2.0V) in single-transistor cells to smaller swings (NFET: -0.35V to supply voltage, PFET: supply voltage to ground). This parameter change reduces transistor stress while maintaining acceptable charge transfer ratios through the complementary transistor pair.
2Reliability
If a CMOS DRAM cell uses dual transistors with separate word lines, then transistor stress is reduced, but the capacitance on the bit line doubles reducing charge transfer ratio and retention
Solution Approach 1:
The patent inverts the conventional CMOS DRAM approach by using a single shared bit line instead of separate bit lines for NFET and PFET. This inversion reduces the total bit line capacitance from doubled capacitance to single capacitance, improving charge transfer ratio and retention while the dual-transistor complementary structure continues to reduce transistor stress.
3Ease of operation
If the bit line is precharged to ground, then the NFET body leaks high causing degradation to off current and retention, but precharging to supply voltage causes PFET body to leak low
Solution Approach 1:
The patent introduces a body contact structure as an intermediary element that provides independent control over the NFET and PFET bodies. This mediator allows the bit line to be precharged to either ground or supply voltage without suffering from body leakage effects, as the body contacts prevent the leakage paths that would otherwise occur in SOI devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces stress on transistors, maintains charge transfer efficiency, and improves retention time by utilizing both bit lines for write operations, enhancing the overall performance of the memory circuit.
Implementation Method 1
An n-type field-effect transistor (NFET) access transistor selected by a first word line couples the storage capacitor to one of the pair of bit lines. A p-type field-effect transistor (PFET) access transistor selected by a second word line couples the storage capacitor to another of the pair of bit lines.
Data Source
AI summary
A complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell with sense amplifier is described. In one embodiment, the DRAM cell includes an n-type field-effect transistor (NFET), a p-type field-effect transistor (PFET), and a storage capacitor accessed through both the NFET and the PFET. A pair of bit lines is coupled to the DRAM cell. A sense amplifier with a single-ended read path reads data in the DRAM cell through only one of the bit lines and a data-dependent write-back path writes back data to the DRAM cell through either one of the bit lines. The bit line used by the sense amplifier to write back the data to the DRAM cell depends on the logical value of the data.