Semiconductor Memory Refresh Control via Auto-Precharge Signals
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Solution Overview
Problem
Volatile semiconductor memory apparatuses require improved refresh operations to effectively retain stored data, with existing technologies not adequately addressing the need for efficient precharge and recovery processes during refresh operations.
Innovation Solution
A semiconductor memory apparatus with a row address control block and bank control block that generate specific signals for auto-precharge and pre-bank active operations in response to refresh signals, enabling precharge and refresh operations without external commands, and ensuring recovery to the pre-refresh state post-operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed in volatile semiconductor memory apparatuses, then data retention is improved, but operational complexity and time consumption increase due to required precharge and recovery processes
Solution Approach 1:
The patent applies preliminary action by performing precharge operations before refresh operations are needed. The row address control block automatically generates precharge signals in advance, ensuring that memory banks are prepared for upcoming refresh operations without requiring external precharge commands, thus simplifying the overall operational complexity while maintaining data retention reliability
Solution Approach 2:
The patent implements self-service through the automatic generation of precharge and recovery signals by the row address control block. The system serves itself by internally managing the precharge and recovery processes without external intervention, automatically detecting when refresh operations are needed and executing the necessary preparatory and restorative actions, thereby reducing operational complexity while ensuring data retention
2Reliability
If precharge and recovery processes are performed during refresh operations, then data retention is improved, but operation time increases
Solution Approach 1:
The patent reduces operation time by performing precharge actions in advance before refresh operations are triggered. The row address control block anticipates refresh needs and initiates precharge sequences proactively, so that when refresh operations commence, the memory banks are already prepared, eliminating delays and reducing overall operation time while maintaining data retention reliability
Solution Approach 2:
The patent maintains continuity of useful action by overlapping precharge operations with ongoing memory access operations where possible. The automatic precharge mechanism operates continuously in the background, preparing banks for future refresh operations without interrupting current productive operations, thus minimizing the impact on overall operation time while ensuring data retention through timely refresh operations
Data Source
AI summary
A semiconductor memory apparatus may include a row address control block configured to output an address as a row address or output a counted signal as the row address in response to a refresh signal and the address, and generate an auto-precharge signal and a pre-bank active signal in response to the refresh signal and a bank active signal. The semiconductor memory apparatus may include a bank control block configured to generate the bank active signal in response to an active signal, a precharge signal, a bank address signal, the auto-precharge signal and the pre-bank active signal.