Semiconductor Memory Addressing Circuit Bypasses Redundancy Comparison
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Solution Overview
Problem
Existing semiconductor memory devices require time-consuming address comparisons for redundancy operations, which slow down data addressing and redundancy processes due to the need to identify and reroute data around defective cell arrays.
Innovation Solution
An addressing circuit and method that bypasses the need for address comparisons by using a series of register units, where data is either stored or passed through based on defect information, with control signals generated by content addressable memory latches and clock generators to determine whether data is stored in normal or defective cell arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address comparison is performed for redundancy operation, then defective cell arrays can be identified and repaired, but processing time increases
Solution Approach 1:
The patent applies preliminary action by pre-storing defect information in CAM latches before the addressing operation. When data is written, the control unit immediately checks the CAM latch to determine if the target cell array is defective, eliminating the need for real-time address comparison. This pre-prepared defect information allows the system to quickly route data to redundant cell arrays without time-consuming comparisons during the actual redundancy operation.
Solution Approach 2:
The patent extracts the address comparison function from the redundancy operation process by using separate CAM latches to store defect information. The control unit extracts only the necessary defect status from the CAM latch without performing full address comparisons, separating the defect identification function from the data routing function to reduce processing time.
2Productivity
If sequential data input is implemented without address comparison, then processing speed improves, but data must be routed around defective cell arrays
Solution Approach 1:
The patent applies segmentation by dividing the register units into multiple stages (first register unit, second register unit, third register unit) with different functions. The first register unit handles normal data storage, the second handles defective cell array bypassing, and the third handles redundant cell array storage. This segmentation allows sequential data input to proceed at high speed while the segmented register units collectively manage the complexity of routing around defective cell arrays.
Solution Approach 2:
The patent uses the second register unit as an intermediary that receives data from the first register unit and conditionally passes it to the third register unit when the target cell array is defective. This intermediary register unit mediates the data flow, enabling sequential processing to continue without interruption while handling the complexity of defective cell array bypassing through controlled data passing.
Data Source
AI summary
The addressing circuit of a semiconductor memory device includes a plurality of register units coupled to an input unit and a plurality of memory cell arrays, wherein the plurality of register units are configured to store inputted data in response to register control signals, and a control unit configured to generate the register control signals, using defect information of respective memory cell arrays, to control whether or not the register units store the inputted.