Non-Volatile Resistive Switches with Varistors for Voltage Stress
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Solution Overview
Problem
Integrated circuits face challenges with volatile memory elements, such as SRAM and CRAM cells, due to scaling issues leading to decreased read/write margins and increased sensitivity to PVT variations, especially at lower power supply voltages, which can result in reduced memory yield and susceptibility to soft error upsets.
Innovation Solution
The use of non-volatile resistive memory elements, such as programmable metallization cells (PMCs) or conductive-bridging RAM (CBRAM), which are configured in a back-to-back arrangement with access transistors, providing immunity to soft error upsets and reducing the voltage stress on driver circuits by splitting the programming voltage between positive and negative voltages, allowing the use of thin gate oxide transistors and minimizing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistors are scaled to smaller sizes and lower threshold voltages to improve integration density, then device size and power consumption are reduced, but read/write margins for volatile memory elements decrease
Solution Approach 1:
The patent transitions from volatile memory (SRAM/CRAM) to non-volatile resistive memory (PMC/CBRAM), fundamentally changing the memory type parameter. This allows the system to use smaller transistors while maintaining adequate write margins through the inherent properties of resistive switching mechanisms that don't depend on tight voltage margins like volatile memory does.
Solution Approach 2:
The patent replaces the volatile memory mechanism (cross-coupled inverters with address transistors) with a non-volatile resistive switching mechanism. This substitution eliminates the need for continuous power supply and complex read/write operations, allowing simpler and smaller transistor designs while maintaining reliability.
2Use of energy by moving object
If power supply voltage is reduced to lower power consumption, then energy efficiency improves, but memory yield decreases due to increased sensitivity to PVT variations
Solution Approach 1:
The patent changes the memory technology parameter from volatile to non-volatile resistive memory, which has different electrical characteristics that are less sensitive to PVT variations. This allows operation at lower voltages while maintaining yield because resistive switching thresholds are more stable against process and temperature variations compared to CMOS inverter-based memory.
Solution Approach 2:
The patent employs a simplified memory cell structure with fewer transistors (replacing the 6T SRAM cell with a resistive switch and access transistor), reducing the impact of PVT variations on overall memory array yield. The non-volatile nature also eliminates the need for refresh operations, improving effective yield.
3Speed
If volatile memory elements are used to provide fast access, then speed is improved, but susceptibility to soft error upsets increases
Solution Approach 1:
The patent replaces volatile memory cells with non-volatile resistive memory elements that use physical material state changes (conductive filament formation/dissolution) to store data. This substitution provides inherent soft error immunity because the stored state is physically encoded in the resistive material rather than being held in vulnerable capacitor or inverter states that can be easily upset by cosmic rays or radiation.
Solution Approach 2:
The non-volatile resistive memory elements maintain their stored state without external power or refresh operations, providing automatic protection against soft errors. The memory state persists in the material structure itself, eliminating the need for continuous stabilization that makes volatile memory susceptible to radiation-induced upsets.
4Reliability
If non-volatile resistive memory elements are used to improve reliability and soft error immunity, then resistance to PVT variations and soft errors increases, but programming requires higher voltage that may exceed transistor breakdown limits
Solution Approach 1:
The patent segments the programming voltage function by introducing separate write enable transistors (thick oxide) dedicated to voltage delivery during programming operations. This segmentation allows the main access transistors to operate at low voltages for normal read operations while the write enable transistors handle the high voltage stress during programming, isolating the stress to specific components designed for it.
Solution Approach 2:
The patent applies different oxide thickness qualities to different transistor locations: thin oxide transistors are used for low-voltage read operations and data storage, while thick oxide transistors are used specifically for high-voltage programming operations. This local differentiation of quality allows the system to achieve both low-power operation and high-voltage programming capability without compromising reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability and immunity to soft error upsets, reduces circuit area, and maintains oxide reliability criteria by using thin gate oxide transistors while providing non-volatile behavior and zero standby current, making integrated circuits more suitable for applications requiring robustness against cosmic and radioactive interference.
Implementation Method 1
A varistor may be used to limit a voltage across a non-volatile resistive memory element during programming of the non-volatile resistive memory element. The varistor may prevent a gate oxide breakdown voltage of a transistor
Data Source
AI summary
Integrated circuits with an array of programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive memory elements connected in series and two varistors. A first of the two varistors is used to program a top resistive memory element in the resistive switch element, whereas a second of the two varistors is used to program a bottom resistive memory element in the resistive switch element. Row and column drivers implemented using only thin gate oxide transistors are used to program a selected resistive switch in the array without violating a maximum voltage level that satisfies predetermined defects per million (DPM) reliability criteria.