Multi-path Semiconductor Memory with Occupancy Signaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-processor systems, existing DRAM memory structures are inefficient due to single input/output paths, making it difficult to achieve sufficient data transmission rates and increasing system complexity and cost, especially in portable communication devices where multiple processors require shared memory access with accurate occupancy state signaling.
Innovation Solution
A semiconductor memory device with a shared memory area and multiple ports allows processors to selectively access the shared memory area, featuring an occupancy state signaling unit that outputs port occupancy state information to indicate access availability, enabling efficient access management and reducing system complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single input/output path is used in DRAM memory structure, then the device complexity is reduced, but the data transmission rate becomes insufficient
Solution Approach 1:
The patent divides the single input/output path into multiple independent paths (first I/O path and second I/O path), allowing simultaneous data transmission through different routes. This segmentation enables multiple processors to access the memory concurrently, increasing the overall data transmission rate while maintaining manageable complexity through modular path design.
Solution Approach 2:
The patent transitions from a single-dimensional access path to a multi-dimensional access structure by adding parallel I/O paths. This dimensional expansion allows data to flow through multiple independent channels simultaneously, effectively increasing the data transmission capacity without proportionally increasing the complexity of each individual path.
2Area of stationary object
If multiple processors share a single DRAM through complex bus interfaces, then the system size is reduced, but the system complexity and cost increase
Solution Approach 1:
The patent creates a universal memory access structure where the shared DRAM can be accessed by multiple processors through standardized multi-path interfaces. Each processor can utilize any of the available I/O paths, making the memory system multi-functional and adaptable to different processor configurations without requiring custom interface designs for each processor-memory connection.
Solution Approach 2:
The patent introduces an occupancy state signaling mechanism that acts as an intermediary between processors and the shared memory. This signaling system mediates access requests by providing occupancy state information, enabling processors to coordinate their access to the shared DRAM without complex arbitration logic, thereby reducing overall system complexity while maintaining compact size.
3Speed
If processors access shared memory without occupancy signaling, then the access speed is increased, but the access reliability decreases due to conflicts
Solution Approach 1:
The patent implements an occupancy state signaling system that provides feedback information to processors about the current state of the shared memory. The memory device signals its occupancy state (busy or available) back to the processors, enabling them to adjust their access timing accordingly. This feedback mechanism maintains high access speeds by avoiding unnecessary waiting while ensuring reliability through conflict prevention.
Solution Approach 2:
The patent enables processors to perform preliminary checks of the occupancy state signal before initiating memory access operations. By checking the occupancy state in advance, processors can determine whether the shared memory is available for immediate access or if they should wait, thereby preventing access conflicts before they occur and maintaining both speed and reliability.
Data Source
AI summary
A multi-path accessible semiconductor memory device having a shared memory area in a DRAM memory cell array that can be randomly accessed by a plurality of processors is provided. The multi-path accessible semiconductor memory device includes at least one shared memory area allocated in a memory cell array, operably connected to ports corresponding to a plurality of processors, each port used by the corresponding processor to selective access the shared memory area. The device further comprises an occupancy state signaling unit to output port occupancy state information to the processor requesting access to the shared memory area through the port used for the access request to indicate whether access to the shared memory area is allowed.