Dynamic Frequency Clock Synchronization for DRAM
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Solution Overview
Problem
Dynamic random access memory (DRAM) faces challenges in synchronizing main clock and data clock signals at high operation frequencies, leading to insufficient aligning margins for clock synchronization, resulting in potential misalignment and data loss during high-speed data interfaces.
Innovation Solution
A memory device with a clock synchronizing circuit that receives a data clock signal with a dynamic frequency, featuring a preamble period with one clock frequency and a data input/output period with a different frequency, generates division clock signals, and selectively outputs these as internal data clock signals based on a clock synchronization signal to ensure synchronization between the main and data clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operation frequency of DRAM is increased, then the data transfer speed is improved, but the aligning margin of setup time or hold time is reduced, causing clock synchronization failure
Solution Approach 1:
The patent applies dynamics by making the data clock signal frequency variable rather than fixed. The data clock signal transitions from a first frequency during the preamble period to a second frequency during the data input/output period. This dynamic frequency adjustment allows the system to achieve high-speed data transfer while maintaining adequate setup and hold time margins for reliable clock synchronization between the main clock and data clock domains.
2Productivity
If the operation frequency of DRAM is increased, then the productivity is improved, but the aligning margin is reduced, leading to potential data loss
Solution Approach 1:
The patent applies preliminary action by introducing a preamble period before the actual data input/output operation. During this preamble period, the data clock signal operates at a lower first frequency, allowing the clock synchronizing circuit to establish proper synchronization between clock domains in advance. This preliminary synchronization ensures that when the high-speed data transfer begins, the aligning margins are sufficient to prevent data loss and maintain data integrity.
3Device complexity
If a fixed frequency data clock signal is used, then the device complexity is reduced, but the clock synchronization margin is insufficient at high speeds
Solution Approach 1:
The patent implements a dynamic frequency data clock signal that automatically adjusts between two frequencies based on the operational phase. This dynamic approach enhances clock alignment reliability during high-speed operations without requiring complex additional synchronization circuits, as the frequency adjustment itself provides the necessary timing margins.
Solution Approach 2:
The patent employs periodic action by structuring the data clock signal to operate in distinct periodic phases: a preamble period at the first frequency for synchronization, followed by a data input/output period at the second frequency for high-speed transfer. This periodic structure inherently provides timing margins during the transition and operation phases, ensuring reliable clock synchronization without adding device complexity.
Data Source
AI summary
A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.