Memory Read Circuit Segmentation for Error Reduction
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Solution Overview
Problem
Next-generation memory devices face challenges in preventing read errors when reading data from selected memory cells, particularly due to variations in cell currents associated with different resistance states.
Innovation Solution
The memory device incorporates a read circuit that compares the cell current of a selected memory cell with a reference current during a single read period, generating read data based on whether the cell current has a constant or oscillating level, thereby determining the resistance state of the memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional read methods are used to read data from memory cells, then the read operation is simple and fast, but read errors occur when the sensing margin between resistance states is insufficient
Solution Approach 1:
The read circuit is segmented into multiple comparison units, each capable of independent current comparison operations. This segmentation allows the system to perform multiple comparison operations sequentially or in parallel, improving read accuracy through repeated verification while maintaining modular circuit design that limits overall complexity.
Solution Approach 2:
The patent performs more comparison operations than the minimum single comparison would provide. By conducting M comparison operations (where M > 1) between the cell current and reference current, the system achieves excessive verification that ensures accurate detection of resistance states even when sensing margins are small, thereby improving reliability at the cost of additional operational steps.
2Quantity of substance
If the sensing margin between resistance states is small, then the memory device can achieve higher density, but read errors increase
Solution Approach 1:
The read circuit incorporates feedback mechanisms where the results of comparison operations are fed back into the decision-making process. By performing multiple comparisons and using the accumulated results to determine the final read data, the system provides feedback verification that compensates for small sensing margins, enabling accurate reads even when memory cells are densely packed with reduced resistance state differentiation.
Solution Approach 2:
The patent changes the parameter of comparison operations from a single static comparison to multiple dynamic comparisons. By varying the number of comparison operations and potentially adjusting comparison thresholds based on observed current levels, the system adapts to small sensing margins caused by high density, maintaining read accuracy despite reduced physical separation between resistance state distributions.
3Reliability
If multiple comparison operations are performed to improve read accuracy, then read reliability increases, but the read time increases
Solution Approach 1:
The multiple comparison operations are structured as periodic actions with regular time intervals between them. This periodic structure allows the read circuit to efficiently schedule comparisons, potentially overlapping with other circuit operations or utilizing idle time periods, thereby minimizing the overall time penalty while still achieving the reliability benefits of multiple comparisons.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes read errors by accurately detecting the resistance state of memory cells, even when the sensing margin between resistance states is not sufficiently secured, thereby enhancing the reliability of read operations.
Implementation Method 1
each of the plurality of memory cells configured to store a data value corresponding to read data to be read out
Implementation Method 2
compare a cell current flowing through a selected memory cell among the plurality of memory cells with a reference current during a single read period
Data Source
AI summary
Memory devices and operating methods are disclosed. In an embodiment, a memory device may include a memory cell array including a plurality of memory cells, each of the plurality of memory cells configured to store a data value corresponding to read data to be read out through a plurality of conductive lines, and a read circuit connected to the plurality of conductive to generate the read data corresponding to the data value stored in a selected memory cell among the plurality of memory cells based on or according to whether there is a change in a cell current flowing through the selected memory cell during a single read period.