Sense Amplifier Timing for Edge Memory Array Utilization
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Solution Overview
Problem
In dynamic random-access memory (DRAM) device arrays, the edge memory array sections have unused memory cells due to interleaved row segments, where only half of the memory cells are utilized, leading to inefficient use of space.
Innovation Solution
The edge memory array sections are configured to use all memory cells by splitting digit lines and forming sense amplifiers in the gap between them, with DL jumpers connecting half digit line pairs to form extended lines that connect to inner memory array sense amplifiers, and adjusting sense amplifier activation timing and threshold voltage compensation to accommodate different digit line lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If interleaved row segments are used in edge memory array sections, then sense amplifier operation is simplified, but memory cell utilization efficiency deteriorates
Solution Approach 1:
The memory array is divided into inner array mats and edge array mats, with each edge array mat further segmented into multiple row segments. This segmentation allows different timing schemes to be applied to different segments, enabling full utilization of edge memory cells while maintaining simplified sense amplifier operation through consistent segment-based organization.
Solution Approach 2:
The patent implements dynamic timing control where sense amplifiers are activated at different times based on their location (inner vs. edge array mats) and the specific row segment being accessed. This dynamic timing adjustment allows all memory cells including edge cells to be fully utilized while maintaining operational simplicity through automated timing management.
2Area of stationary object
If border row segments are used in edge memory array sections, then array edge coverage is improved, but area efficiency deteriorates due to unused memory cells
Solution Approach 1:
The patent extends the memory array organization into multiple dimensions by creating interleaved row segments that wrap around array edges. This multi-dimensional organization allows border row segments to be fully utilized by accessing them through different row segment sections, converting previously wasted edge area into productive storage space.
Solution Approach 2:
The patent changes the operational parameters of edge memory cells by implementing different sense amplifier activation timings and row segment selection schemes for edge versus inner arrays. This parameter differentiation allows all edge memory cells to be actively used while maintaining overall system efficiency through optimized timing and access patterns.
Data Source
AI summary
A memory hank has banks of sense amplifiers positioned in edge memory array mats that are coupled to digit lines with different lengths than banks of sense amplifiers coupled between inner memory array mats. During a main sense phase of a sense operation, a first sense amplifier bank positioned between an edge memory array mat and an inner memory array mat is activated at a first time prior to activation of a second sense amplifier bank positioned in the edge memory array mat at a second time.