Switching Buffer Layout for Semiconductor Data Path Timing

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Solution Overview

Problem

Existing semiconductor device layouts face issues with data input/output timing shifts between memory cell array regions, increased number of necessary shield lines, and varying data input/output timing depending on operation modes, which limit access speed and reduce design flexibility due to the need for data buses to pass through regions occupied by address control and command decoder circuits.

Innovation Solution

The semiconductor device incorporates a layout with strategically arranged memory cell arrays and data buses, utilizing switching buffers to optimize data transfer paths and reduce the number of shield lines required, allowing for consistent data arrival times across different operation modes and improved access speed by alternating data bus configurations to function as shields for each other.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data buses are arranged to connect memory cell array regions, then data transfer capability is provided, but data input/output timing shifts between memory cell array regions occur

Engineering Contradiction:

Improvedata transfer capabilityVSAvoiddata input/output timing consistency

Core Design Contradiction:

SpeedVSManufacturing precision

Solution Approach 1:

Switching buffers are introduced as intermediary components between memory cell array regions and data terminals. These buffers act as mediators that receive data from multiple memory cell array regions and selectively transfer it to appropriate data terminals, thereby equalizing data input/output timing across different regions and eliminating timing shifts while maintaining data transfer capability

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The data bus system is segmented into multiple independent data terminals (first data terminal, second data terminal) that can be independently configured. Memory cell array regions are also segmented and assigned to different data terminals based on their spatial locations, allowing each segment to operate with optimized timing characteristics

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If data buses are routed through address control and command decoder circuit regions, then connectivity is achieved, but the number of necessary shield lines increases

Engineering Contradiction:

Improvedata bus routing flexibilityVSAvoidnumber of shield lines

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The semiconductor device is divided into distinct functional regions: memory cell array regions at corners, switching buffer regions at mid-points of sides, and data terminal regions. This segmentation allows data buses to be routed through dedicated switching buffer regions rather than passing through address control and command decoder circuit regions, reducing the need for shield lines while maintaining routing flexibility

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The layout transitions from a two-dimensional planar arrangement to a more distributed three-dimensional spatial configuration. Memory cell array regions are positioned at corners, switching buffers at mid-points of sides, and data terminals at specific locations, creating multiple spatial dimensions for data bus routing that avoid congested areas and reduce shielding requirements

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Productivity

If memory cell array regions are divided and data buses are arranged between them, then access speed is improved, but timing shifts depending on operation modes occur

Engineering Contradiction:

Improveaccess speedVSAvoidtiming consistency across operation modes

Core Design Contradiction:

ProductivityVSStability of the object's composition

Solution Approach 1:

Switching buffers are configured to dynamically change their connection states based on different operation modes (first operation mode, second operation mode). In each mode, the switching buffers selectively connect to different data terminals, allowing the data bus configuration to adapt dynamically while maintaining consistent timing characteristics across all operation modes

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The switching buffers serve multiple functions: they act as data transfer intermediaries, timing equalizers, and mode-dependent configurators. The same switching buffer infrastructure supports both first operation mode and second operation mode with consistent timing performance, providing universal functionality across different operational requirements

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9978438B2Device having multiple switching buffers for data paths controlled based on IO configuration modes

Publication Date: 2018.05.22 MICRON TECHNOLOGY INC

AI summary

A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are arranged such that a distance between the first switching buffer and the second data terminal is shorter than a distance between the second switching buffer and the second data terminal and that a distance between the first switching buffer and the first data terminal is shorter than a distance between the second switching buffer and the first data terminal.