SRAM Write Assist Circuit for Low-Voltage Stability
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Solution Overview
Problem
As semiconductor technology scales down, SRAM chips face increased fault rates and inefficiencies in write operations due to reduced supply voltage near the minimum threshold voltage (Vcc-min), particularly in bit cells far from the power source, where bit line resistance aggravates voltage reduction and discharging inefficiency.
Innovation Solution
Incorporating write assist devices on bit lines, connected in-line between the bit lines and ground, with gates controlled by separate write assist signals to drive voltages effectively during write operations, reducing transmission line effects by ensuring both ends of the bit lines are driven to the appropriate voltage, effectively cutting inline resistance in half.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If supply voltage is reduced to conserve power and reduce leakage current, then energy efficiency is improved, but write operation speed and stability deteriorate due to inefficient discharging near Vcc-min
Solution Approach 1:
A write assist circuit is introduced as an intermediary component between the bit line and ground. This circuit includes a write assist transistor that provides an additional discharging path during write operations, enabling efficient voltage discharge even when the main supply voltage is near Vcc-min. The write assist circuit acts as a mediator that compensates for the insufficient discharging capability caused by low supply voltage, thus maintaining write speed while allowing low-power operation.
2Use of energy by moving object
If supply voltage is reduced to conserve power, then energy efficiency is improved, but write operation stability deteriorates near Vcc-min
Solution Approach 1:
The write assist circuit serves as a stability-enhancing intermediary by providing a controlled additional discharge path. During write operations, the write assist transistor is activated to ensure adequate discharging, preventing unstable states that would occur with insufficient voltage discharge near Vcc-min. This intermediary mechanism guarantees reliable write operations while maintaining the low supply voltage regime for power efficiency.
3Productivity
If bit line resistance increases due to scaling down, then manufacturing efficiency is improved, but voltage applied to peripheral bit cells is further reduced, aggravating write inefficiency
Solution Approach 1:
The write assist circuit implements local quality by providing targeted assistance at the peripheral bit cells where the problem is most severe. The write assist transistor is strategically placed and controlled to compensate for the voltage drop caused by bit line resistance in remote cells. This localized intervention ensures that peripheral bit cells receive adequate discharge capability despite the increased bit line resistance from scaling, maintaining write reliability across the entire memory array.
4Area of stationary object
If geometry size is decreased to increase functional density, then chip area utilization is improved, but bit line resistance increases, aggravating voltage reduction in peripheral cells
Solution Approach 1:
The write assist circuit addresses the harmful effect of increased bit line resistance through local quality enhancement. By placing write assist transistors at strategic locations and activating them for peripheral bit cells, the circuit locally compensates for the resistance-induced voltage drop. This allows the design to maintain small geometry sizes for high density while mitigating the adverse effects of increased bit line resistance in peripheral regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances write speed and stability by reducing transmission line effects and maintaining adequate power supply to SRAM bit arrays, even at minimum voltage levels, without increasing peripheral circuitry size or complexity.
Implementation Method 1
Incorporating write assist devices on bit lines, connected in-line between the bit lines and ground, with gates controlled by separate write assist signals to drive voltages effectively during write operations, reducing transmission line effects by ensuring both ends of the bit lines are driven to the appropriate voltage, effectively cutting inline resistance in half
Data Source
AI summary
A static random-access memory (SRAM) semiconductor device including a memory unit is provided. The memory unit includes a bit array arranged in rows and columns. The columns are defined by a plurality of bit line pairs connecting to a plurality of memory cells in the column. The memory unit also includes an edge area adjacent an edge row of the bit array, wherein the edge row includes a plurality of dummy memory cells. The memory unit further includes a plurality of bit line drivers adjacent the bit array and opposite the edge area. The bit line drivers are for driving the bit lines with data to the memory cells during a write operation. The dummy memory cells include a write assist circuit for each bit line pair. The write assist circuit is used for facilitating the writing of the data on the bit line pairs to the memory cells.