Semiconductor Driving Method for Oxide Transistor Data Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices using oxide semiconductors face challenges in preventing incorrect data reading and maintaining high reliability due to off-state current issues and power consumption, especially during data retention and reading operations.
Innovation Solution
A driving method for semiconductor devices is introduced, utilizing a configuration with n-channel and p-channel transistors, including an oxide semiconductor film in the channel formation region, where the potential of the bit line is set to specific values to prevent incorrect data reading, and the use of a capacitor enhances data retention and reading operations by controlling the gate potential of the second transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is retained by keeping the first transistor off, then data retention is achieved, but off-state current leakage may cause incorrect data reading
Solution Approach 1:
The patent introduces a second transistor as an intermediary between the first transistor and the bit line. This second transistor acts as a mediator that controls the connection between the storage node and the bit line, preventing direct leakage paths while allowing controlled data reading. The intermediary transistor isolates the storage node from leakage effects on the bit line.
Solution Approach 2:
The patent changes the potential parameter of the bit line to a specific second potential V2 during data retention. This parameter change optimizes the electrical conditions to minimize leakage current effects and maintain stable data storage. By adjusting the bit line potential, the patent creates optimal conditions for reducing off-state current impact.
2Reliability
If the bit line potential is set to prevent leakage, then data retention improves, but power consumption increases
Solution Approach 1:
The patent employs periodic action by setting the bit line potential to the second potential V2 only during specific operations (data retention and reading), rather than maintaining it continuously. This periodic application of the optimized potential reduces overall power consumption while achieving the desired data retention and reading accuracy during critical operation windows.
3Productivity
If the third transistor is turned on for reading, then data retrieval is enabled, but leakage current may affect reading accuracy
Solution Approach 1:
The second transistor serves as an intermediary that mediates between the first transistor and the bit line during reading operations. When the third transistor is turned on for reading, the second transistor controls the signal flow and potential distribution, preventing leakage current from directly affecting the bit line and thereby maintaining reading accuracy while enabling fast data retrieval.
Solution Approach 2:
The patent utilizes parameter changes by setting the bit line to the second potential V2 during reading operations. This parameter optimization ensures that when the third transistor is activated for fast reading, the electrical conditions are optimized to maintain both high reading speed and high accuracy by minimizing leakage effects.
Data Source
AI summary
In a memory cell including first to third transistors, the potential of a bit line is set to VDD or GND when data is written through the first transistor. In a standby period, the potential of the bit line is set to GND. In reading operation, the bit line is brought into a floating state at GND, and a source line is set to a potential VDD−α, consequently, the third transistor is turned on. Then, the potential of the source line is output according to the potential of a gate of the second transistor. Note that α is set so that the second transistor is surely off even when the potential of the gate of the second transistor becomes lower from VDD by ΔV in the standby period. That is, Vth+ΔV<α is satisfied where Vth is the threshold value of the second transistor.