MRAM Array Perpendicular Source Bitline Architecture
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Solution Overview
Problem
Conventional MRAM array density is limited by minimum pitch width, hindering further increases in memory density and performance while maintaining reliability, as fabrication techniques advance.
Innovation Solution
Implementing a perpendicular source and bit line architecture in MRAM arrays, where the source line is held at zero voltage and the write bias voltage goes from high to low, allowing for a tighter pitch without reducing the pitch width below minimums, and utilizing a sacrificial circuit element to provide desired voltage to the common source line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional parallel source lines and bit lines are used in MRAM arrays, then each cell can be independently addressed and written, but the pitch width between traces increases, limiting array density
Solution Approach 1:
Multiple memory cells share a common source line, merging what were previously separate source lines into a single trace. This reduces the number of traces required in the array, thereby reducing the pitch width between traces and enabling higher array density without compromising the ability to independently address and write to each cell through the bit line and word line control mechanism
Solution Approach 2:
The patent transitions from a conventional planar arrangement where source lines and bit lines are parallel to a perpendicular arrangement where source lines extend vertically while bit lines extend horizontally. This dimensional change allows for tighter spacing and higher density while maintaining independent cell access through the gating transistor controlled by word lines
2Quantity of substance
If fabrication process sizes are reduced to increase memory density, then more cells fit in a given die area, but the minimum pitch width between traces is reduced below acceptable limits
Solution Approach 1:
By merging multiple source lines into a single common source line that serves multiple cells, the patent reduces the total number of traces that must be fabricated. This decreases the minimum pitch width requirement between traces, allowing the use of smaller fabrication process sizes to achieve higher memory density without running into trace width limitations
Solution Approach 2:
The common source line serves multiple memory cells simultaneously, making it a universal trace that performs the source function for several cells. This multi-functionality reduces the overall trace count and allows for reduced pitch width while maintaining proper electrical isolation and control through the gating transistors and word lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased MRAM array density and performance while maintaining reliability, allowing for more memory per unit area with reduced power consumption and costs, by eliminating the need for dual parallel bit and source lines.
Implementation Method 1
Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell change due to the orientation of the magnetic fields of the two layers
Implementation Method 2
The electrical resistance is typically referred to as tunnel magnetoresistance (TMR) which is a magnetoresistive effect that occurs in a MTJ
Implementation Method 3
If a spin-polarized current is passed to the magnetic region of a free layer in the MTJ device, the electrons will transfer a portion of their spin-angular momentum to the magnetization layer to produce a torque on the magnetization of the free layer
Data Source
AI summary
A memory device comprising an array of memory cells wherein each memory cell includes a respective magnetic random access memory (MRAM) element, and a respective gating transistor. A plurality of bit lines are routed parallel to each other, wherein each bit line is associated with a respective memory cell of the array of memory cells. A common word line is coupled to gates of gating transistors of the array of memory cells. A common source line is coupled to sources of the gating transistors, wherein the common source line is routed perpendicular to the plurality of bit lines within the array of memory cells. A sacrificial circuit element is coupled to a sacrificial bit line, coupled to the common word line and coupled to the common source line, wherein the sacrificial circuit element is operable to provide a desired voltage to the common source line wherein the desired voltage originates from the sacrificial bit line.