I/O Functional Unit Multiplexer Latch Architecture
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Solution Overview
Problem
Existing memory technologies face challenges in efficiently utilizing chip area for built-in self-test (BIST) circuits, particularly in configuring latches within I/O functional units to facilitate reliable read and write operations while minimizing capacitive loading and optimizing performance during both normal and test modes.
Innovation Solution
The implementation of a two-tier multiplexer system with latches in I/O functional units, where multiplexers select bitlines from two groups, reducing capacitive loading and allowing latches to be configured as a scan chain during test mode, enabling efficient data readout and testing of peripheral circuits without affecting bitcell array operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If latches in I/O functional units are configured into a scan chain during test mode, then test efficiency is improved, but device complexity increases
Solution Approach 1:
The latches are designed to dynamically reconfigure between two operational modes: normal I/O functional mode during memory operations and scan chain mode during testing. This dynamic reconfiguration allows the same hardware structure to serve dual purposes, improving test efficiency while minimizing the increase in device complexity through mode-switching rather than dedicated test hardware
Solution Approach 2:
The I/O functional unit latches are designed with multi-functionality to operate both as data latches during normal memory operations and as scan chain elements during testing. This universal design allows a single component to fulfill multiple functions, achieving high test efficiency without requiring separate dedicated test hardware that would increase device complexity
2Object-generated harmful factors
If a two-tier multiplexer system is implemented, then capacitive loading is reduced, but device complexity increases
Solution Approach 1:
The multiplexer system is segmented into two tiers: a first tier of multiplexers that select between bitlines and a second tier that selects between the first tier outputs and additional inputs. This segmentation divides the capacitive loading burden across multiple stages rather than having a single large multiplexer, reducing overall capacitive loading while the modular structure manages device complexity through organized hierarchy
Solution Approach 2:
The selection process is extended from a single-dimensional direct select to a two-dimensional hierarchical select structure. The first tier handles bitline selection and the second tier handles additional input selection, creating a layered approach that reduces capacitive loading by distributing the selection burden across dimensions rather than concentrating it in a single multiplexer stage
Data Source
AI summary
A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.