Fine-Grain 3D Memory Device Logic Base Layer Footprint Reduction
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Solution Overview
Problem
Existing 3D memory devices suffer from unfavorable footprint and performance due to their stacked configuration, which requires logic circuits in every layer for selecting memory units, leading to inefficient routing and increased footprint.
Innovation Solution
The proposed fine-grain 3D memory device architecture separates the selection logic for memory layers, allowing for independent selection of logic tech nodes for logic and memory layers. This is achieved by placing a logic base layer with demultiplexers and multiplexers at the bottom, with memory units stacked above, reducing the need for logic circuits in every memory layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If logic circuits are placed in every memory layer for selecting memory units, then memory unit selection capability is improved, but device footprint and routing complexity increase
Solution Approach 1:
The patent segments the memory device into distinct functional layers: a logic base layer containing all selection logic circuits (demultiplexers and multiplexers) and separate memory layers containing only memory units. This segmentation allows the selection capability to be concentrated in the base layer while memory layers remain compact, resolving the contradiction between selection capability and footprint area.
Solution Approach 2:
The patent utilizes vertical stacking to separate logic and memory functions into different z-dimensions. The logic base layer is positioned at the bottom while memory layers are stacked above, allowing independent optimization of each layer's footprint without requiring lateral expansion for routing circuits throughout the device.
2Ease of operation
If logic circuits are distributed across all layers, then memory unit accessibility is improved, but routing length and complexity increase
Solution Approach 1:
The patent extracts all logic circuits (demultiplexers and multiplexers) from the memory layers and relocates them to the logic base layer. This extraction eliminates the need for complex inter-layer routing of control signals, significantly reducing routing length while maintaining full memory unit accessibility through the base layer's selection logic.
Solution Approach 2:
The logic base layer acts as an intermediary between external control signals and the stacked memory layers. All address and control signals are routed through the base layer's demultiplexers and multiplexers, which then selectively activate specific memory units, simplifying the overall routing architecture compared to distributed logic circuits.
Data Source
AI summary
A 3D memory device is provided. The 3D memory device includes a first logic base layer, a second layer, and a third layer. The first logic base layer comprises a first type DEMUX, a plurality of second type DEMUXs coupled to the first type DEMUX, a first type MUX, and a plurality of second type MUXs coupled to the first type MUX. The second layer comprises a first group of memory units. Each of the first group of memory units is respectively coupled to a corresponding DEMUX of the plurality of second type DEMUXs and a corresponding MUX of the plurality of second type MUXs. The third layer comprises a second group of memory units. Each of the second group of memory units is respectively coupled to a corresponding DEMUX of the plurality of second type DEMUXs and a corresponding MUX of the plurality of second type MUXs.