Configuration Bit Architecture for Programmable ICs
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Solution Overview
Problem
As device feature sizes decrease, it becomes increasingly difficult to implement stacked transistors in programmable integrated circuit devices without a large area penalty due to the challenge of isolating nodes between stacked transistors, leading to increased leakage and power consumption.
Innovation Solution
The solution involves intentionally interconnecting the shared nodes of adjacent configuration memory cells in an alternating pattern, where the interconnected nodes will either leak or not leak based on the configuration bit stored, predominantly reducing leakage when most cells store zeroes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If stacked pull-up or pull-down transistors are implemented in configuration memory cells, then leakage is reduced, but device area increases due to difficulty in isolating nodes between stacked transistors
Solution Approach 1:
The patent merges the shared nodes of stacked transistors from adjacent configuration memory cells into a common interconnect structure. By connecting the shared nodes of stacked pull-up transistors (or stacked pull-down transistors) across multiple cells, the design eliminates the need for isolation structures between cells, reducing area while maintaining leakage reduction benefits
Solution Approach 2:
The shared node interconnect structure serves multiple functions: it acts as the shared node for stacked transistors in each cell, provides leakage reduction across all connected cells, and eliminates the need for separate isolation structures. This multi-functional approach reduces overall device area
2Quantity of substance
If device feature sizes decrease, then integration density increases, but node isolation between stacked transistors becomes increasingly difficult
Solution Approach 1:
By merging shared nodes across adjacent cells into common interconnects, the patent eliminates isolation requirements that would otherwise be necessary at each cell boundary, making the design more manufacturable at smaller feature sizes
3Ease of manufacture
If configuration memory cells use non-interconnected shared nodes, then node isolation is simplified, but leakage increases
Solution Approach 1:
The patent converts the potentially harmful effect of interconnected nodes (which could create leakage paths) into a beneficial structure by using the interconnects to share nodes in a way that actually reduces leakage. The alternating connection pattern ensures that leakage reduction is achieved while maintaining manufacturability
Data Source
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AI summary
An array of memory cells on an integrated circuit device includes a plurality of memory cells arranged in at least one column. Each of the memory cells includes a plurality of transistors forming two complementary memory nodes. Each of the complementary memory nodes is connected to a respective pair of pull-up or pull-down transistors, which are connected in series and have a shared node between them. For a particular one of the memory cells, one of the shared nodes associated with one of the complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a second one of the memory cells, and another of the shared nodes associated with another of the complementary memory nodes is directly connected to a corresponding shared node associated with a corresponding complementary memory node in a third one of the memory cells.