Semiconductor Memory Device Partial Write Mechanism
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Solution Overview
Problem
Semiconductor memory devices, particularly phase change random access memory, experience high power consumption and reduced lifespan due to frequent access in write mode, necessitating a method to minimize accessed memory cells and extend their lifespan.
Innovation Solution
A semiconductor memory device design that includes a memory cell array, a storage circuit for pattern data, a data input circuit, a comparison circuit, and a write circuit, which writes only the differing data values from normal write data to the memory cell array based on comparison signals, thereby reducing the number of accessed memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If normal write data is written to all memory cells in write mode, then data integrity is maintained, but power consumption increases and memory cell lifespan decreases
Solution Approach 1:
The patent extracts only the necessary portion of write data that differs from pattern data and writes only that extracted data to the memory cell array. The comparison circuit identifies differences between normal write data and pattern data, and the write circuit writes only to memory cells corresponding to differing data values, thereby reducing power consumption while maintaining data integrity for the extracted portion.
Solution Approach 2:
Instead of writing all normal write data to all memory cells, the patent applies partial action by writing only to the extent necessary - specifically, only to memory cells where the data differs from the stored pattern data. This partial writing approach reduces the number of accessed memory cells and associated power consumption while ensuring data integrity for the modified portions.
2Reliability
If normal write data is written to all memory cells in write mode, then complete data update is achieved, but the number of accessed memory cells increases reducing lifespan
Solution Approach 1:
The patent extracts only the necessary portion of write data that differs from pattern data and writes only that extracted data to the memory cell array. The comparison circuit identifies differences between normal write data and pattern data, and the write circuit writes only to memory cells corresponding to differing data values, thereby reducing power consumption while maintaining data integrity for the extracted portion.
Solution Approach 2:
Instead of writing all normal write data to all memory cells, the patent applies partial action by writing only to the extent necessary - specifically, only to memory cells where the data differs from the stored pattern data. This partial writing approach reduces the number of accessed memory cells and associated power consumption while ensuring data integrity for the modified portions.
3Use of energy by moving object
If comparison circuit is added to reduce writes, then power consumption decreases, but device complexity increases
Solution Approach 1:
The comparison circuit serves multiple functions: it compares normal write data with pattern data to identify differences, generates comparison signals that control the write operation, and enables the partial write mechanism. This multi-functionality justifies the added complexity by providing comprehensive control over the write operation to reduce power consumption.
Solution Approach 2:
The comparison circuit acts as an intermediary between the data input circuit and the write circuit. It processes the normal write data and pattern data to generate comparison signals that mediate the write operation, determining which memory cells should be updated. This intermediary function enables intelligent write control while maintaining a clear separation of concerns in the data path.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a storage circuit suitable for storing pattern data, a data input circuit suitable for receiving normal write data from an external device, a comparison circuit suitable for comparing the pattern data with the normal write data based on a pre-read control signal, and generating a comparison signal corresponding to the comparison result, and a write circuit suitable for writing the pattern data to the memory cell array based on a pre-write control signal, and writing some of the normal write data to the memory cell array based on a normal write control signal and the comparison signal.