Memory Access Circuit with Wait State Counter
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Solution Overview
Problem
Memory access times in computing devices are affected by varying process, voltage, and temperature (PVT) conditions, leading to performance degradation and increased power consumption, especially in memory circuits with significant PVT variations.
Innovation Solution
A method and apparatus utilizing a wait state counter and synchronizer to provide a synchronized data ready signal, ensuring data readiness regardless of PVT conditions by counting predetermined clock cycles and synchronizing asynchronous memory ready signals, thereby minimizing memory access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory access time is reduced to improve performance, then device speed increases, but reliability under varying PVT conditions deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal wait state values in a lookup table before operation. The PVT compensation circuit queries this table using measured PVT parameters to immediately retrieve pre-determined compensation values, avoiding complex real-time calculations and ensuring reliable access time compensation across varying conditions.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the wait state counter value based on measured PVT conditions. The system modifies the number of wait states inserted into the memory access cycle according to temperature, voltage, and process variations, thereby maintaining consistent access times despite changing environmental parameters.
2Reliability
If wait states are increased to compensate for slow memory circuits under certain PVT conditions, then reliability improves, but device complexity increases
Solution Approach 1:
The patent uses an intermediary approach by introducing a PVT compensation circuit that acts as a mediator between the memory circuit and the controller. This intermediary measures PVT parameters, queries a lookup table for compensation values, and automatically adjusts wait states, thereby simplifying the overall system architecture while maintaining reliability under varying conditions.
Solution Approach 2:
The system applies self-service by enabling the memory access control to automatically compensate for PVT variations without external intervention. The PVT compensation circuit autonomously measures environmental parameters, retrieves compensation values from the lookup table, and adjusts wait states independently, reducing the need for complex external control logic.
3Reliability
If PVT compensation mechanisms are implemented to maintain consistent access times, then reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies partial action by implementing compensation only for the most significant PVT parameters that have the greatest impact on memory access time. The system measures and compensates for temperature, voltage, and process variations to the extent necessary to achieve acceptable access time consistency, avoiding the need for ultra-precise measurement and control of all possible parameters.
Data Source
AI summary
According to an aspect, there are provided an apparatus and a method for providing an access to a memory circuit. A read enable input initializing a wait state counter configured to count a predetermined number of clock cycles is received (200) and the wait state counter output is monitored. A memory ready signal output is received (202) from the memory circuit at a synchronizer input and the output signal of the synchronizer is monitored. An ON-state data ready signal is provided (204) when either the wait state counter has elapsed, or the output signal of the synchronizer is in ON-state.