Write Assist Circuit for SRAM Voltage Control
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Solution Overview
Problem
Conventional SRAM cells face challenges in efficient data writing operations due to high drain-to-source leakage currents and slow voltage transitions, which affect the speed and reliability of memory cell operations.
Innovation Solution
A write assist circuit is introduced, which adjusts operational voltages by applying bias voltage differences to the memory cell's transistors during write operations, optimizing voltage levels to enhance transistor switching speeds and reduce leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional SRAM cell structure is used, then device complexity is low, but data writing speed is slow and leakage currents are high
Solution Approach 1:
A write assist circuit is introduced as an intermediary component between the bit line and the SRAM cell. This circuit includes a write assist transistor connected to the bit line and a first node of the SRAM cell, and a write assist inverter connected to the first node and a second node. The write assist circuit mediates the write operation by controlling voltage transitions at the SRAM cell nodes, thereby improving write speed without requiring fundamental changes to the core SRAM structure.
Solution Approach 2:
The write assist circuit dynamically adjusts voltage parameters during write operations. By controlling the write assist transistor and inverter, the circuit creates voltage differences between nodes to accelerate charge transfer. This parameter-based control enables faster switching of the SRAM cell transistors during write operations, directly improving data writing speed while maintaining the conventional SRAM cell architecture.
2Object-generated harmful factors
If conventional SRAM cell structure is used, then manufacturing simplicity is maintained, but leakage currents are high
Solution Approach 1:
The write assist circuit acts as an intermediary that controls the voltage levels at the SRAM cell nodes during write operations. By properly managing voltage transitions through the write assist transistor and inverter, the circuit prevents unintended leakage currents from flowing through the SRAM cell transistors, thereby reducing harmful leakage effects without altering the basic cell structure.
Solution Approach 2:
The write assist circuit performs preliminary voltage preparation before the actual write operation. By pre-establishing appropriate voltage conditions at the SRAM cell nodes through the write assist inverter and transistor, the circuit ensures that leakage currents are minimized during the subsequent write operation, as the transistors are already in the optimal state for low-leakage operation.
3Speed
If conventional SRAM cell structure is used, then structural simplicity is maintained, but voltage transitions are slow
Solution Approach 1:
The write assist circuit serves as an intermediary that accelerates voltage transitions at the SRAM cell nodes. The write assist transistor and inverter work together to create steeper voltage ramps and faster transitions by controlling the charging and discharging paths. This intermediary approach enables faster voltage transitions without requiring changes to the SRAM cell's fundamental structure.
Solution Approach 2:
The write assist circuit dynamically changes voltage parameters to accelerate transitions. By controlling the write assist inverter and transistor, the circuit creates optimized voltage profiles that reduce transition time. The circuit adjusts voltage levels and rates during the write operation, enabling faster node transitions while maintaining the simplicity of the conventional SRAM cell architecture.
Data Source
AI summary
A device is disclosed to include a memory cell, a first write assist unit and a second write assist unit. The first write assist unit provides a first operational voltage at a first pair of terminals of the memory cell. The second write assist unit provides at a second pair of terminals of the memory cell a second operational voltage different from the first operational voltage. In a write operation of the memory cell, the first write assist unit further generates a voltage difference between the first pair of terminals.