DRAM Data Resetting via State Machine Signal Extension
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Solution Overview
Problem
Dynamic random access memory (DRAM) lacks the ability to encrypt data, making it vulnerable to data theft, and existing resetting methods only manage state machine resets without performing actual data resets, leading to security compromises and error correction issues.
Innovation Solution
A data resetting method for DRAM that involves providing a state machine resetting signal for a predetermined time, disabling sense amplifiers, and applying specific voltages to bit lines and word lines to reset memory cells, allowing for consistent data resetting across odd and even word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a state machine resetting signal is provided to reset the state machine inside the DRAM, then the state machine can be reset, but the actual data in memory cells cannot be reset, leading to security compromises and error correction issues
Solution Approach 1:
The patent applies preliminary action by disabling sense amplifiers before applying the resetting voltage to bit lines. This ensures that the voltage applied to bit lines is not amplified and distorted by the sense amplifiers, allowing clean data resetting. The sense amplifier disable step is performed in advance to prepare the memory array for the upcoming data reset operation.
Solution Approach 2:
The patent changes the voltage parameter applied to bit lines from normal operating voltages to a specific resetting voltage (first voltage or second voltage) that is different from regular read/write voltages. This parameter change enables the bit lines to function as data reset carriers rather than their normal signal transmission function, achieving data resetting without requiring new pin specifications.
2Reliability
If sense amplifiers are enabled during data resetting operation, then normal reading function is maintained, but the resetting voltage applied to bit lines will be amplified and cause inconsistent data reset across different word lines
Solution Approach 1:
The patent segments the word lines into odd-numbered and even-numbered groups, resetting them in separate phases. During the first phase, sense amplifiers are disabled and first voltage is applied to bit lines while odd-numbered word lines are enabled. Then sense amplifiers are enabled and even-numbered word lines are enabled for the second phase. This segmentation allows different voltage levels to be applied to different word line groups without interference from sense amplifier amplification.
Solution Approach 2:
The patent implements periodic action by alternating between disabling and enabling sense amplifiers in synchronized phases with the word line selection. The sense amplifiers are disabled during the voltage application phase and enabled during the reading phase, creating a periodic pattern that ensures clean voltage transfer to bit lines while maintaining reading functionality.
3Reliability
If the state machine resetting signal duration is extended, then data resetting operation can be performed, but the time required for reset increases
Solution Approach 1:
The patent performs preliminary actions by disabling sense amplifiers and applying resetting voltage to bit lines before enabling word lines for data resetting. This preliminary preparation ensures that when data resetting is needed, the memory array is already configured to receive and store the reset voltage efficiently, reducing the overall reset time.
Solution Approach 2:
The patent maintains continuity of useful action by keeping the state machine resetting signal extended for a predetermined time period that covers both the sense amplifier disable phase and the data resetting operation. This continuous signal extension ensures that the data resetting operation can proceed without interruption and complete within the predetermined time window.
Data Source
AI summary
A random access memory data resetting method is provided. The method includes following steps. First, a state machine resetting signal is provided to a RAM. Next, the state machine resetting signal is extended for a predetermined time period. Afterwards, a data resetting operation is executed in the RAM within the predetermined time period.