Address Transition Detecting Circuit Noise Immunity
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Solution Overview
Problem
Existing address transition detecting (ATD) circuits in asynchronous SRAM systems are vulnerable to noise-induced burrs on address lines, leading to unstable pulse widths that can result in delayed or failed write and read operations.
Innovation Solution
The proposed solution involves an ATD circuit design using two unilateral delay circuits and NAND or NOR gates to control the pulse width at both the rising and falling edges of the address signal, ensuring the pulse width is determined by the delay time and not by noise-induced burrs, thereby stabilizing the ATD signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay circuit is used to generate pulse signals for address transitions, then the pulse width can be controlled to enable proper pre-charging and word-line activation, but the pulse width becomes vulnerable to noise-induced burrs on the address line causing unstable timing
Solution Approach 1:
The patent divides the address transition detection into two independent paths: one for rising edges and one for falling edges. Each path has its own delay circuit and NAND gate, allowing independent control and stabilization of pulse widths for each transition type, preventing noise in one path from affecting the other.
Solution Approach 2:
The patent introduces an intermediary delay circuit between the address signal and the NAND gate input. This delay circuit acts as a buffer that filters out high-frequency noise and burrs while allowing the essential transition information to pass through, stabilizing the pulse width generation.
2Speed
If the pulse width is made narrow to speed up operations, then read operation speed improves, but pre-charging of bit-lines becomes insufficient leading to operation failures
Solution Approach 1:
The patent dynamically adjusts the pulse width parameter based on the specific transition type (rising or falling edge) and the required operation (read or write). By using separate delay circuits for each transition type, the system can optimize pulse widths for different scenarios rather than using a fixed narrow pulse that may be insufficient for pre-charging.
3Reliability
If the pulse width is made wide to ensure sufficient pre-charging, then bit-line pre-charging is complete, but the pulse causes delay in write or read operations
Solution Approach 1:
The patent applies different pulse width characteristics to different parts of the operation sequence. The rising edge path and falling edge path have different delay characteristics optimized for their specific functions, allowing each transition to have the appropriate pulse width for its purpose rather than a uniform wide pulse for the entire operation.
Data Source
AI summary
The address transition detecting circuit includes two identical address transition detecting signal generating module, an inverter and a signal combining module. Both of the two address transition detecting signal generating modules have a unilateral delay circuit for generating an output pulse at the rising edge of the address signal and an output pulse at the falling edge of the address signal. The address transition detecting signal generating module can control the width of the two output pulses by controlling the delay times of the corresponding unilateral delay circuit. The signal combining module outputs the ATD signal having pulses at both the rising edge and falling edge of the address signal. The present application uses two unilateral delay circuits to control the width of the ATD signal at the rising edge and the falling edge of the address signal, thereby significantly preventing the width of the ATD signal from influence of the burr on the address line.