Ferroelectric Gate Stack Tunnel Dielectric Insert for NAND Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing 3D NAND flash technology faces challenges in achieving a large enough memory window (MW) to support multi-bit operation while maintaining the thickness constraints of the ferroelectric gate stack, which affects the scalability and efficiency of the technology.
Innovation Solution
Incorporating a tunnel dielectric layer (TDL) within the ferroelectric gate stack, which divides the ferroelectric layer into separate regions, effectively enhancing the memory window by leveraging trap dynamics and dipole engineering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the ferroelectric layer is increased to enhance memory window, then the memory window increases, but the thickness limit of 3D-NAND is exceeded and ferroelectricity is lost
Solution Approach 1:
The ferroelectric layer is divided into multiple thinner ferroelectric sub-layers separated by tunnel dielectric layers. This segmentation allows the total memory window to be accumulated across multiple interfaces while each individual ferroelectric sub-layer remains within the thickness limit to maintain ferroelectricity. The tunnel dielectric layers with trap states contribute additional memory window at each interface.
Solution Approach 2:
The gate stack employs a composite structure combining multiple ferroelectric materials and tunnel dielectric materials. The tunnel dielectric layers contain trap states that work synergistically with the ferroelectric layers to enhance the overall memory window. This composite approach allows achieving higher memory window without increasing the total thickness beyond 3D-NAND limits.
2Reliability
If the thickness of the ferroelectric layer is increased to achieve theoretical maximum memory window, then memory window approaches 2Ec*tf, but practical MW is limited to ≤3 V due to charge injection and trapping effects
Solution Approach 1:
Tunnel dielectric layers are introduced as intermediary layers between the ferroelectric layers. These tunnel dielectric layers contain trap states that act as mediators to manage charge injection and trapping effects. The traps in the tunnel dielectric layers capture excess charges that would otherwise degrade the memory window, thereby protecting the ferroelectric layers and enabling practical MW to exceed the conventional 3V limit.
Solution Approach 2:
The invention converts the harmful charge trapping effects into a beneficial mechanism. By intentionally introducing trap states in the tunnel dielectric layers, these traps serve to stabilize the ferroelectric polarization states and enhance the memory window. The charge trapping that would normally be harmful is now utilized to create additional memory window through the trap-assisted tunneling and polarization control mechanisms.
3Quantity of substance
If Z-pitch scaling is aggressive to enable massive bit cell density, then bit cell density increases, but gate control is reduced and write voltage increases
Solution Approach 1:
The invention changes the electrical parameters of the gate stack by introducing tunnel dielectric layers with specific trap densities and energy levels. This parameter change enables achieving the same or higher memory window with lower write voltages. The trap states in the tunnel dielectric layers assist in polarization switching at lower voltages, thereby reducing the power requirement for write operations while maintaining high bit cell density achieved through Z-pitch scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The insertion of the tunnel dielectric layer significantly increases the memory window, enabling multi-bit operation while maintaining the thickness limits of the NAND technology, thereby enhancing the scalability and efficiency of the ferroelectric gate stack.
Implementation Method 1
effectively enhancing the memory window by leveraging trap dynamics and dipole engineering
Implementation Method 2
effectively enhancing the memory window by leveraging trap dynamics and dipole engineering
Implementation Method 3
the plurality of ferroelectric layers including a first ferroelectric layer and a second ferroelectric layer
Data Source
AI summary
A ferroelectric gate stack may include a semiconductor layer, a conductor layer facing the semiconductor layer, a plurality of ferroelectric layers spaced apart from each other between the semiconductor layer and the conductor layer, a tunnel dielectric layer between a first ferroelectric layer and a second ferroelectric layer among the plurality of ferroelectric layers, and an interface layer between the semiconductor layer and the first ferroelectric layer.