3T DRAM Memory Cells for In-Memory Logic Without Latch Overhead
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Solution Overview
Problem
Conventional DRAM memory cells require additional latches for data inversion during logical operations, leading to increased power consumption and read-to-read delays due to destructive read operations.
Innovation Solution
Implementing 3T DRAM memory cells that can invert data without additional latches, allowing logical operations to be performed directly within the memory cells, reducing the need for external processing resources and minimizing data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional DRAM memory cells are used for logical operations, then data inversion requires additional latches, but this increases device complexity and power consumption
Solution Approach 1:
The patent merges the data inversion function with the memory cell structure itself by utilizing the complementary nature of bit line and complement bit line signals. The memory cell inherently produces both true and complement outputs, eliminating the need for separate latches to perform inversion operations. This integration reduces device complexity and associated power consumption.
Solution Approach 2:
The memory cell performs inversion operations on its own output signals without requiring external latch circuits. The complement bit line naturally provides the inverted signal, allowing the memory cell to serve its own inversion needs and reducing overall system complexity.
2Ease of operation
If additional latches are used for data inversion, then logical operations can be performed, but read-to-read delays increase
Solution Approach 1:
The complement bit line is prepared in advance as part of the normal memory cell operation, containing the inverted data ready for immediate use in logical operations. This preliminary preparation eliminates the need for additional inversion steps that would cause delays between read operations.
3Loss of information
If destructive read operations are used, then data can be read from memory cells, but the data must be refreshed or rewritten
Solution Approach 1:
The patent uses the complement bit line as a copy of the original data in inverted form. This copying mechanism allows the inverted data to be used for logical operations without destroying the original data in the memory cell, enabling non-destructive reads and improving processing efficiency.
4Reliability
If data must be refreshed after read operations, then data integrity is maintained, but processing performance decreases
Solution Approach 1:
The memory cell structure is designed to simultaneously provide both true and complement outputs without requiring separate refresh operations. This multi-functionality allows the same cell to serve multiple purposes (data storage and inversion) without compromising data integrity or requiring additional refresh cycles that would reduce processing performance.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.