Logic Circuits Characterised By Logic Function TRIZ Cases

A layered magnetic heterojunction independently controls in-plane and out-of-plane exchange bias, enabling stable spin logic and multiple-state storage.

Interlayer exchange coupling enables a magnetic multiplier cell to hold binary results at room temperature without continuous power.

Staggered clock gating keeps a second charge pump off during power-up, reducing peak current overlap and protecting components.

A resistor-capacitor backup supply keeps the inverter active during brief voltage dips, improving SoC power-glitch attack detection.

An air-gap structure widens the Schottky barrier in 2D logic gates, improving on-off ratio and stable electron-hole switching.

Air-gap and Schottky-barrier tuning suppress ambipolar conduction in 2D semiconductors, enabling stable inverter and AND/OR logic switching.

Using a refresh-charged capacitor and discrete inductor, this case shows how laser diode drivers create ultra-short high-current pulses at lower voltage.

Dual monitoring of undercurrent and negative-sequence overcurrent isolates broken three-phase lines before ground faults or short circuits develop.

Star-connected transformer secondaries in a three-phase LLC circuit cut switching current, voltage stress, and primary RMS current.

A signal is routed through only one matching die circuit, saving third-die area, reducing power, and avoiding extra mask costs in 3D IC stacks.

Using one gate line pitch across standard cells with different gate widths keeps alignment regular and eases automated layout and OPC.

A switchable PFC and converter setup adapts power by operating mode to meet THD limits for multimedia and lighting without oversizing the supply.

Logic, op-amps, and MOSFETs shut down unnecessary BMS components during idle periods to limit battery pack drain and avoid overdischarge.

Temperature-based mode switching lets a memory voltage pump use single, dual, or mixed stages to meet VPP needs with less wasted power.