Backup-Powered Inverter Circuit for Short Power-Glitch Detection

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Solution Overview

Problem

Current power-glitch detection systems in system-on-chip (SoC) designs face challenges in accurately detecting malicious power-glitch attacks due to weak discharging capabilities of MOSs during short glitch durations, leading to potential failure in identifying such attacks.

Innovation Solution

The implementation of a chip with a power terminal, a first inverter, and a back-up power storage device, which includes a resistor and capacitor in series, coupled to the inverter to provide back-up power during glitches, and a latch or D flip-flop for detecting power glitches, with a reset circuit to reset the detection unit for subsequent glitches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If MOS discharging capability is used for power-glitch detection, then the detection system can operate with simple circuitry, but the detection reliability fails during short glitch durations

Engineering Contradiction:
Improvepower-glitch detection reliabilityVSAvoidglitch detection time window
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent applies preliminary action by pre-charging capacitors (first and second capacitors) before a power glitch occurs. When a glitch happens, these pre-charged capacitors can immediately discharge to pull the output nodes to opposite logic levels, enabling detection within the short glitch duration. The back-up power storage device also provides preliminary energy storage to sustain the inverter operation during the glitch.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements beforehand cushioning by introducing a back-up power storage device connected to the inverter. This back-up power source acts as a cushion that maintains power supply to the inverter during voltage dips caused by power glitches, allowing the detection circuit to remain operational and detect the glitch event reliably.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Use of energy by moving object

If lower supply voltages are used in SoC chips, then power consumption is reduced, but power-glitch detection accuracy deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidpower-glitch detection accuracy
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent uses capacitors as intermediary energy storage elements that decouple the detection circuit's operation from the fluctuating power supply. The capacitors store energy and provide stable voltage levels to the inverter output nodes during glitches, enabling accurate detection even when the main power supply operates at lower voltages with higher susceptibility to glitches.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the operational parameters of the detection circuit by using back-up power storage to maintain sufficient voltage levels at the inverter outputs during glitches. This allows the circuit to maintain detection accuracy despite the overall lower supply voltage environment in modern low-power SoC designs.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enhances the detection of power glitches by ensuring reliable and timely identification, even with lower supply voltages, by using back-up power to quickly react to glitches and maintaining accurate output levels, thereby improving the security of SoC chips against malicious attacks.

Implementation Method 1

The back-up power storage device has a resistor and a capacitor which are connected in series

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

The first inverter is powered by the back-up power when a power glitch occurs on the power terminal, and the power glitch is reflected at an output terminal of the first inverter

Methodology Applied
Scientific EffectInversion:

Implementation Method 3

The latch further has a first capacitor coupling the positive output terminal to the power terminal to pull up the voltage level of the positive output terminal after the power glitch

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11916432B2Chip with power-glitch detection
Publication Date: 2024.02.27 MEDIATEK INC
  • US11916432B2 patent drawing
  • US11916432B2 patent drawing
  • US11916432B2 patent drawing

AI summary

A chip with power-glitch detection is provided, which includes a power terminal receiving power, an inverter, and a back-up power storage device coupled to the power terminal. The inverter has an input terminal coupled to the power terminal. The back-up power storage device transforms the power to back-up power. The inverter is powered by the back-up power when a power glitch occurs on the power terminal, and the power glitch is reflected at an output terminal of the inverter.