3T DRAM Read Bit Line Segmentation for Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current DRAM memory devices face limitations in configuration and operation, particularly in signal routing on the back side of a semiconductor substrate, which affects performance and efficiency.
Innovation Solution
The proposed solution involves a DRAM array configuration with two read bit lines in each column, reducing capacitance and increasing read current, along with shared read word lines between adjacent DRAM cells, to enhance read speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single read bit line is used for each column in conventional DRAM arrays, then the device complexity is reduced, but the read speed is limited due to higher capacitance and lower read current
Solution Approach 1:
The patent divides the single read bit line into two separate read bit lines (first read bit line and second read bit line) for each column. This segmentation reduces the capacitance on each individual bit line, allowing higher read current and faster read speeds. Each bit line is connected to different DRAM cells, enabling parallel read operations that improve overall read performance.
2Productivity
If read bit lines are separated into multiple lines, then read current increases and read speed improves, but the routing complexity and device complexity increase
Solution Approach 1:
The patent utilizes the back side of the semiconductor substrate to route signal lines, adding a spatial dimension to the routing architecture. By routing read bit lines and word lines on the back side, the design achieves better signal separation and reduced interference without significantly increasing front-side routing complexity. This dimensional approach allows for cleaner signal paths and improved read efficiency.
Solution Approach 2:
The read bit lines are segmented into multiple separate lines that are routed on the back side of the substrate. This segmentation reduces capacitance and allows for independent optimization of each bit line's routing path, improving read efficiency while managing routing complexity through systematic organization.
3Quantity of substance
If more DRAM cells are added to increase memory capacity, then the memory device can hold more data, but the signal routing becomes more complex and read speed decreases
Solution Approach 1:
By segmenting read bit lines into multiple separate lines and connecting them to different DRAM cells, the patent enables parallel read operations. This segmentation allows the system to maintain high read speeds even as memory capacity increases, because multiple read operations can occur simultaneously on different bit lines without interfering with each other.
Solution Approach 2:
Routing signal lines on the back side of the substrate provides an additional spatial dimension for signal distribution. This allows for more efficient routing as memory capacity increases, maintaining signal integrity and read speed by distributing signals across multiple layers and paths rather than congesting the front side routing.
Data Source
AI summary
A memory device includes a memory array having a first memory cell in a first column of the memory array, a second memory cell in the first column of the memory array, a first read bit line extending in a column direction and connected to the first memory cell to read data from the first memory cell, and a second read bit line extending in the column direction and connected to the second memory cell to read data from the second memory cell.