Digital Storage TRIZ Cases
- Signal Compensation Circuit for Semiconductor Stability
A signal compensation circuit combines delayed and direct signals to stabilize column strobe pulse widths in semiconductor apparatuses.
- Pipelined Output Latching for Synchronous Memory Arrays
A pipelined output latching system with reduced register count and optimized clock alignment using Delayed Lock Loop circuits.
- 3T DRAM Read Bit Line Segmentation for Speed
Segmenting read bit lines in a 3T DRAM array reduces line capacitance, which increases read current to resolve speed limitations caused by high signal load.
- DRAM Bit Line Shielding for Parasitic Capacitance Reduction
Shield conductor layer embedded in sidewall insulation reduces parasitic capacitance on DRAM bit lines.
- DRAM Sense Amplifier Boosting Circuit Low Power Sensing
A DRAM sense amplifier uses boosting circuits to increase voltage differences between bit lines during precharge operations.
- Memory Controller Row Hammer Mitigation via Adjacent Refresh
A memory controller selects adjacent addresses for refresh operations to mitigate row hammer disturbances in dynamic random access memory arrays.
- Semiconductor Memory Row Decoder Sharing Control Blocks
Shared control blocks reduce unit row decoder area by merging address latches and controllers, resolving space constraints for higher mat counts.