Semiconductor Memory Row Decoder Sharing Control Blocks
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in increasing the number of mats due to limited space for unit row decoders, as the area required for these decoders increases with the number of mats, and integrating more devices while maintaining high-speed operation is difficult.
Innovation Solution
A semiconductor memory device design that includes common control blocks to simultaneously control multiple row decoders, reducing the need for individual controller areas and integrating redundancy cells within a fuse group, along with a peripheral circuit group for row address latch signals, allowing for increased mat integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of mats is increased, then the memory capacity is improved, but the area required for unit row decoders increases
Solution Approach 1:
The patent merges multiple unit row decoder groups into a shared row decoder structure. Specifically, multiple mat rows share common control blocks including the row address latch decoder, row address latch, and row decoder controller, eliminating the need for separate controller units in each row decoder group. This consolidation reduces the total decoder area while maintaining the capability to decode addresses for multiple mats.
Solution Approach 2:
The shared row decoder is designed with universal functionality to serve multiple mat rows simultaneously. The single row address latch decoder and row decoder controller can selectively decode addresses for any of the shared mat rows through control signals, making the decoder structure multi-functional rather than dedicated to a single mat row.
2Quantity of substance
If more devices are integrated, then the memory capacity is improved, but the device complexity increases
Solution Approach 1:
The patent combines multiple decoder functions into a unified shared row decoder structure. By merging the row address latch decoders, row address latches, and row decoder controllers into shared resources, the overall device complexity is reduced compared to having separate dedicated decoders for each mat row.
Solution Approach 2:
The shared row decoder is organized into modular segments that can independently serve different mat rows. The decoder structure is divided into shareable control blocks and mat-specific selection logic, allowing the system to manage complexity through modular design while maintaining high integration.
3Area of stationary object
If the area of unit row decoders is reduced, then the mat integration density is improved, but the operational speed may be compromised
Solution Approach 1:
By consolidating multiple row decoder controllers into a single shared controller, the patent reduces the total decoder area while maintaining operational speed through efficient control signal distribution. The shared controller uses control signals to selectively activate the appropriate mat row, ensuring that speed performance is maintained despite the reduced area.
Solution Approach 2:
The shared row decoder incorporates dynamic control mechanisms that allow it to adaptively select and activate specific mat rows based on address decoding results. This dynamic operation ensures that the reduced decoder area does not compromise speed, as the controller can quickly switch between different mat rows as needed.
Data Source
AI summary
A semiconductor memory device comprises a plurality of banks including a plurality of mat rows, respectively, wherein the mat row includes a plurality of mats disposed in a same row, row decoder groups disposed between the banks and including row decoders that correspond to the mat rows, respectively, and common control blocks installed corresponding to a predetermined number of row decoders to simultaneously control the row decoders.