DRAM Bit Line Shielding for Parasitic Capacitance Reduction
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Solution Overview
Problem
The shrinking size of dynamic random access memory (DRAM) designs leads to increased parasitic capacitance in bit lines, affecting performance, and existing technologies have not effectively addressed this issue.
Innovation Solution
A dynamic random access memory structure is developed with a sidewall structure comprising a first insulation layer, a second insulation layer, and a shield conductor layer, which is electrically connected to an interconnection structure, reducing parasitic capacitance by applying specific voltages during writing and reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of DRAM design continues to shrink toward high integration, then device integration increases, but parasitic capacitance of bit line increases affecting performance
Solution Approach 1:
A shield conductor layer is introduced as an intermediary component between the bit line and surrounding structures. This shield conductor, positioned within a sidewall structure comprising first and second insulation layers, acts as an electromagnetic shield to reduce parasitic capacitance coupling between the bit line and adjacent conductive elements, thereby mitigating the harmful capacitive effects that arise during high-integration scaling
Solution Approach 2:
The sidewall structure employs a composite configuration combining multiple insulation layers with a conductive shield layer. The first insulation layer directly contacts the bit line sidewall, the shield conductor layer is embedded within the composite structure, and the second insulation layer provides additional insulation, creating a multi-material composite solution that simultaneously provides electrical shielding and insulation functions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces resistance capacitance delay (RC-delay) and enhances sensing margins, resulting in higher reliability and suitability for low-power DRAM applications, while being easily integratable with existing manufacturing processes.
Implementation Method 1
The performance of the dynamic random access memory may be affected by the parasitic capacitance of a bit line. Therefore, how to effectively reduce the parasitic capacitance of the bit line has become an important research topic in this field.
Data Source
AI summary
A method of manufacturing a dynamic random access memory including the following steps is provided. A bit line is formed on a substrate. A sidewall structure is formed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. An interconnection structure electrically connected to the shield conductor layer is formed.