Memory Controller Row Hammer Mitigation via Adjacent Refresh
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Solution Overview
Problem
In memory products, repeated access to word lines leads to data damage due to the 'row hammer' effect, where adjacent word lines are disturbed, causing data loss when the number of disturbances exceeds a certain threshold, typically resulting in data damage after 2*10^5 times of disturbance.
Innovation Solution
A memory circuit with a memory controller that counts access instructions and determines when to select an adjacent address as a refresh address for the next refresh operation, thereby mitigating the row hammer effect by refreshing adjacent word lines before they reach the threshold of data damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller performs refresh operation on each memory block at predetermined intervals, then data integrity is maintained, but the victim word line adjacent to frequently accessed word lines becomes disturbed beyond the threshold, causing row hammer effect
Solution Approach 1:
The memory controller performs preliminary refresh operations on adjacent word lines before they reach the disturbance threshold. By monitoring the cumulative access count of neighboring word lines and proactively refreshing adjacent lines, the system prevents row hammer effects before data damage occurs, rather than waiting for the threshold to be exceeded.
Solution Approach 2:
The memory controller implements a feedback mechanism by counting the cumulative number of access instructions for each word line and using this information to dynamically adjust refresh operations. The controller monitors access patterns and adjusts refresh timing based on the disturbance level of adjacent word lines, creating a closed-loop system that adapts to actual usage patterns.
2Reliability
If the memory controller increases refresh frequency to prevent row hammer, then data integrity is improved, but system performance and productivity decrease due to more frequent refresh interruptions
Solution Approach 1:
Refresh operations are performed preliminarily and selectively on only those word lines adjacent to frequently accessed lines, rather than universally refreshing all memory blocks at fixed intervals. This targeted approach maintains data integrity for vulnerable lines while minimizing disruptions to overall system performance.
Solution Approach 2:
The system applies partial refresh action by selectively refreshing only the necessary adjacent word lines based on monitored access patterns, rather than performing excessive full-refresh operations on all memory blocks. This reduces the total number of refresh interruptions while still protecting against row hammer on vulnerable lines.
Data Source
AI summary
A memory circuit is provided. The memory circuit includes a memory array, a plurality of word lines and a memory controller. The memory array has a plurality of memory blocks. The memory controller outputs an access instruction and an access address to address the word lines for accessing the memory array, or the memory controller outputs a refresh instruction and a refresh address to address the word lines for refreshing the memory array, wherein the memory controller performs a refresh operation on each of the memory blocks corresponding to each of the word lines at predetermined intervals. The memory controller counts the number of times the access instructions have been output and determines whether that number equals a predetermined value or not. According to the determination result, the memory controller selects an address adjacent to the access address as the refresh address for the next refresh operation.