4D Processor Mesh Layout for Faster Data Movement
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Solution Overview
Problem
Conventional calculation devices with a two-dimensional mesh structure for processors (PEs) face inefficiencies in data movement, leading to increased time and power consumption due to the need for multiple data transfers between non-adjacent PEs, which hampers calculation speed and power efficiency.
Innovation Solution
A calculation device with processors arranged in a four-dimensional (4D) coordinate system, allowing data input/output with adjacent PEs in X and Y directions and non-adjacent PEs in Z and W directions, reducing the number of required data movements and optimizing wiring length for faster data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If processors are arranged in a two-dimensional mesh structure, then device complexity is reduced and ease of manufacture is improved, but data movement efficiency deteriorates and power consumption increases
Solution Approach 1:
The patent transitions from a conventional two-dimensional mesh structure to a four-dimensional processor arrangement. Processors are organized with coordinates (x, y, z, w) where x and y represent the traditional mesh plane, while z and w represent additional dimensions enabling direct data transfer between non-adjacent processors. This dimensional expansion allows data to move along multiple paths simultaneously, reducing the number of hops required for data communication and thereby lowering power consumption without complicating the manufacturing process.
2Device complexity
If processors are arranged in a two-dimensional mesh structure, then device complexity is reduced, but calculation speed deteriorates due to multiple data transfers
Solution Approach 1:
By adding two more dimensions (z and w) to the traditional two-dimensional mesh, the patent creates a four-dimensional processor network. This allows processors that are not adjacent in the x-y plane to communicate directly by varying the z and w coordinates. Data can now travel along four-dimensional paths, significantly reducing the number of intermediate transfers needed and thereby increasing calculation speed while maintaining manageable device complexity through systematic coordinate organization.
Solution Approach 2:
The four-dimensional space is segmented into multiple coordinate planes and layers. Processors are divided into groups based on their (x, y, z, w) coordinates, allowing data to be routed through different segments of the four-dimensional space. This segmentation enables parallel data paths and reduces contention on any single communication channel, improving overall calculation speed without overwhelming system complexity.
3Ease of operation
If multiple data transfers are performed between non-adjacent processors, then data can reach distant processors, but time consumption increases
Solution Approach 1:
The patent utilizes the four-dimensional coordinate system to create direct data transfer paths between processors that would require multiple hops in a two-dimensional mesh. By adjusting the z and w coordinates, data can jump across the processor network in fewer steps, directly reaching distant processors without traversing through numerous intermediate nodes, thus significantly reducing time consumption while maintaining full data transfer capability.
Solution Approach 2:
The system pre-establishes four-dimensional communication paths between processors during initialization. When data needs to be transferred, the system can immediately utilize these pre-configured paths rather than dynamically routing through multiple intermediate processors. This preliminary setup of data transfer routes reduces the time required for communication across the processor network.
Data Source
AI summary
A calculation device multiple processors. The multiple processors are represented by a coordinate system, which includes two dimensions indicating X direction and Y direction and two or more different dimensions indicating different directions. Each processor is configured to perform data input or data output with the processor adjacent in the X direction or the Y direction, and is further configured to perform data input or data output with the processor adjacent in the different dimension.