Single Instruction Multiple Data Multiprocessors TRIZ Cases
- Multi-Dimensional PE Interconnect for Faster Data Movement
Additional X, Y, Z, and W PE links cut mesh data transfers for sum and max operations, reducing movement steps and power use.
- Neural Processing Core Reconfiguration for Depthwise Convolution
Multiplexer-based data-path switching and adder trees raise depthwise convolution utilization by improving feature-map locality in one NPU core.
- Near-Memory Lattice Accelerator Mapping for Parallel HPC and AI
Compiler-guided mapping across lattice compute and memory modules improves parallel HPC and AI execution while limiting accelerator size.
- SIMD Data Routing Module for Low-Latency Neural Network Shuffling
Dedicated selectors, assemblers, and transfer buffers automate SIMD data rearrangement to cut latency and energy in neural network workloads.
- SIMD Data Routing Module for Low-Latency Memory Rearrangement
Hardware selectors and assemblers rearrange SIMD local-memory data in place, cutting host-driven latency and preserving parallelism.
- Tensor Transposition Layout for Variable-Width AI Memory I/O
Variable memory I/O sizing and tensor transposition improve parallel processing when channel dimensions do not align with fixed vector widths.
- Multi-Dielet GPU Engine Remapping and Memory Barrier Synchronization
Hardware engine remapping and FBHUB memory barriers let multi-dielet GPUs scale beyond single-die limits while preserving a unified software view.
- GPU Neural Network Scheduling for Irregular Kernels
Direct GPU scheduling with a gather unit and relative address table improves handling of irregular kernels and sparse neural network workloads.
- Graph Code API for Locating Incomplete CUDA Capture Sequences
Stream capture APIs identify incomplete graph code locations and manage dependencies to improve graph execution in CUDA environments.
- Hybrid DSP Architecture for In-Memory Vector MAC Processing
A hybrid DSP combines logic-based and in-memory function units to cut data movement and power use in vector matrix operations.
- SIMD Target Function Mapping with Range-Based Approximation
Partitioning target functions into fitted ranges lets SIMD processors balance execution speed and calculation accuracy while reducing error and clock cycles.
- 4D Processor Mesh Layout for Faster Data Movement
A 4D processor arrangement cuts multi-hop transfers in conventional 2D meshes, improving calculation speed and power efficiency.