Hybrid DSP Architecture for In-Memory Vector MAC Processing
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Solution Overview
Problem
Existing digital signal processors (DSPs) face performance limitations in vector matrix multiplication operations, particularly in machine learning and neural network processing, due to the inefficiencies of traditional von Neumann architecture in data movement between operation devices and memory devices.
Innovation Solution
A digital signal processor (DSP) is designed with a hybrid architecture that includes both non-IMC and IMC function units, where non-IMC units use logic gates and IMC units utilize memory cell arrays for operations, supported by a VLIW packetizer and buffer blocks for efficient data transmission, allowing independent processing of instructions across lanes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional von Neumann architecture is used for data movement between operation devices and memory devices, then device complexity is reduced, but processing speed and efficiency deteriorate due to inefficient data movement
Solution Approach 1:
The patent merges the operation unit and memory cell array into a unified in-memory computing function unit, eliminating the need for separate data movement between operation devices and memory devices. This integration allows MAC operations to be performed directly within the memory structure, significantly improving processing speed while managing complexity through functional consolidation.
Solution Approach 2:
The patent introduces a buffer block as an intermediary component between the in-memory computing function unit and the register file. This buffer mediates data transmission, allowing efficient data movement without requiring complex direct connections, thus improving processing speed while keeping the overall architecture manageable.
2Use of energy by moving object
If data is moved between operation devices and memory devices in traditional architecture, then ease of operation is maintained, but power consumption increases due to continuous data movement
Solution Approach 1:
The patent extracts the data movement function from the traditional von Neumann architecture by implementing in-memory computing. MAC operations are performed directly within the memory cell array without requiring data to be moved to separate operation devices, thereby eliminating the power consumption associated with continuous data movement while maintaining operational simplicity through the buffer block.
3Productivity
If in-memory computing is implemented using memory cell arrays, then processing efficiency improves, but device complexity increases due to hybrid architecture requirements
Solution Approach 1:
The patent segments the processing architecture into distinct lanes, with each lane containing a dedicated in-memory computing function unit. This segmentation allows parallel processing of multiple instructions while managing complexity through modular organization. The buffer block further segments data flow management, simplifying the coordination between different functional units.
Solution Approach 2:
The in-memory computing function unit is designed with multi-functionality, capable of performing both MAC operations and serving as a buffer for data transmission. This universality reduces the need for separate dedicated components, thereby improving processing efficiency while managing overall device complexity through functional consolidation.
4Productivity
If multiple function units process instructions independently in parallel lanes, then productivity increases, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent divides the processor into multiple independent lanes, with each lane containing a complete set of function units capable of parallel instruction processing. This segmentation enables high productivity through simultaneous execution of multiple instructions while managing control complexity by giving each lane autonomous control over its own instruction stream.
Data Source
AI summary
Provided are a digital signal processor (DSP) and an electronic device using the same. The DSP includes: a first function unit (FU) having a non-IMC (in-memory computing) operation architecture using an operation unit; a second FU having an IMC architecture using a memory cell array; and a register file used by the first FU and the second FU.