4T0C Cache Device Reducing Latency and Area
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dynamic random access memory (DRAM) components face performance bottlenecks due to bandwidth, data throughput, and latency issues between DRAM and processors, and the manufacturing process is not compatible with advanced logic manufacturing, while SRAM is expensive for large memory capacities.
Innovation Solution
A cache device configuration using a 4T0C architecture with transistors and an inverter, eliminating the need for capacitors, allowing for a DRAM-like configuration compatible with CMOS logic operations, reducing area costs, and increasing memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM components are used, then high density and low cost are achieved, but bandwidth, data throughput, and latency between DRAM and processor become bottlenecks for computing performance
Solution Approach 1:
The patent embeds DRAM cache cells within the logic circuit layer, nesting memory functionality inside the processor architecture. This integration allows the cache to be physically closer to the processing units, enabling faster data access and higher throughput while maintaining high density through efficient space utilization within the same chip footprint.
2Quantity of substance
If standalone DRAM components are used, then high density and low cost are achieved, but distance between DRAM components and processors causes performance bottlenecks
Solution Approach 1:
The patent merges the DRAM cache array with the logic circuit layer, combining previously separate memory and processing components into a unified integrated structure. This merging eliminates the physical distance between DRAM and processor, reducing access latency while maintaining high memory capacity through the integrated architecture.
3Speed
If SRAM is used for large memory capacity, then fast access speed is achieved, but manufacturing cost increases significantly
Solution Approach 1:
The patent changes the manufacturing parameters and materials used in cache construction, adopting DRAM-based technology with different process requirements compared to traditional SRAM. This parameter change enables the use of more cost-effective manufacturing processes while achieving fast access speeds through optimized DRAM cell design and integration architecture.
4Adaptability or versatility
If embedded DRAM or novel devices for L3/L4 caches are used, then compatibility with advanced logic manufacturing is improved, but device complexity increases
Solution Approach 1:
The patent segments the cache structure into modular units with standardized interfaces, dividing the complex cache system into manageable blocks that can be independently manufactured and then assembled. This segmentation reduces overall device complexity by creating repeatable, standardized units that are compatible with advanced logic manufacturing processes while maintaining high performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory performance by reducing latency and increasing memory density, making it compatible with advanced logic manufacturing processes while lowering costs.
Implementation Method 1
the first transistor is turned on and the second transistor is turned off, so that the input voltage is stored in the storage node
Implementation Method 2
The inverter has an input terminal and an output terminal, in which the input terminal is coupled to the storage node
Implementation Method 3
the first transistor is turned off and the second transistor is turned on, and a voltage of the output terminal of the inverter is output as an output voltage through the second terminal of the second transistor
Data Source
AI summary
The disclosure provides a cache device, which includes: a first transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the first transistor is coupled to an input voltage, and the second terminal of the first transistor is coupled to a storage node; an inverter having an input terminal and an output terminal, in which the input terminal is coupled to the storage node; and a second transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the second transistor is coupled to the output terminal of the inverter, and the second terminal of the second transistor is configured to output a read voltage.