5T SRAM Cell Pre-Charge Sensing for Faster Bit Line Split
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Solution Overview
Problem
The semiconductor industry seeks alternatives to traditional 6-transistor static random access memory (SRAM) designs to achieve smaller memory cell sizes and faster performance, as larger caches reduce off-chip memory access and enhance overall IC performance.
Innovation Solution
A 5-transistor SRAM memory cell design is implemented, featuring a P-type pass gate transistor, pre-charge circuit, and differential sensing configuration, which includes a P-type transistor to pull the bit line to a supply voltage during read operations, allowing for a larger bit line split and improved sensing by the sense amplifier without additional voltage or circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional 6-transistor SRAM design is used, then reliability is maintained, but memory cell size is larger and density is lower
Solution Approach 1:
The patent extracts one transistor from the traditional 6-transistor SRAM cell, reducing the transistor count to 5. Specifically, the pass gate transistor is removed and its function is integrated into the load transistor, simplifying the cell structure while maintaining the essential read-write operations through careful circuit design
Solution Approach 2:
The patent merges the function of the pass gate transistor with the load transistor. The load transistor is designed to perform both the traditional load function and the pass gate function, reducing the total transistor count while maintaining circuit functionality through enhanced transistor design
2Speed
If 6-transistor SRAM design is used, then sensing margin is adequate, but sensing time is longer
Solution Approach 1:
The patent changes the electrical parameters of the remaining transistors to compensate for the reduced transistor count. Specifically, the width-to-length ratios of the access and load transistors are optimized to provide sufficient drive current for fast sensing while maintaining adequate sensing margin through precise parameter tuning
3Measurement precision
If additional pre-charge circuitry is added to improve sensing, then sensing performance is enhanced, but device complexity increases
Solution Approach 1:
The patent designs the 5-transistor cell to be self-sufficient for pre-charge operations. The load transistor and access transistors work together to automatically restore the storage nodes to their pre-charge state without requiring external pre-charge circuitry, reducing overall device complexity while maintaining sensing precision
Data Source
AI summary
A memory circuit includes a first and a second bit line, a first and a second inverter, a P-type pass gate transistor, a pre-charge circuit, a first transmission gate and a sense amplifier. The P-type pass gate transistor is coupled between the first storage node and the first bit line. The pre-charge circuit is coupled to at least the first bit line or the second bit line, and configured to charge at least the first or second bit line to a pre-charge voltage responsive to a first signal. The pre-charge voltage is between a voltage of a first logical level and a voltage of a second logical level. The first transmission gate is coupled to the first bit line, and configured to receive a first and a second control signal. The sense amplifier is coupled to the first bit line by the first transmission gate.