6T Bit Cell Compute-in-Memory for CNN Power Reduction
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Solution Overview
Problem
Convolutional neural networks (CNNs) face high power consumption due to memory access and data movement between memory and CPU during dot product operations, which outweighs the power used by the CPU for the operations itself.
Innovation Solution
Implementing a compute-in-memory (CIM) array that stores filter weights and performs computations such as dot product operations directly within the memory, using a multiply and average (MAV) circuit with capacitors and transistors to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If computations are performed by CPU with memory access, then processing capability is maintained, but power consumption increases significantly
Solution Approach 1:
The patent merges the computation function with the memory function by integrating MAV circuits directly into the memory array. Each memory location stores both data and associated computation resources (capacitors and transistors), combining storage and processing operations into a unified in-memory computation architecture that eliminates data movement between separate CPU and memory subsystems.
Solution Approach 2:
The memory array is designed to perform multiple functions: data storage, weight storage for neural networks, and computation execution. The MAV circuits within memory locations can perform multiplication and averaging operations directly where data is stored, making the memory system universally capable of both storage and processing tasks without requiring separate dedicated processing units.
2Productivity
If data movement between memory and CPU is performed, then computations can be executed, but power consumption and time are increased
Solution Approach 1:
The patent performs preliminary actions by pre-storing computation resources (MAV circuits with capacitors and transistors) within memory locations before actual computation is needed. This preliminary configuration of computation capabilities in memory eliminates the need for real-time data movement between CPU and memory during processing operations.
Solution Approach 2:
The memory system performs self-service by executing computations directly within its own structure using integrated MAV circuits. The memory array autonomously performs multiplication and averaging operations on stored data without requiring external CPU intervention or data transfer, making the computation process self-contained within the memory subsystem.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces power consumption by performing computations in-memory, minimizing the need for memory access and data movement, while maintaining efficient processing of CNN operations.
Implementation Method 1
The MAV circuit includes a first capacitor, a second capacitor, a first transistor coupled to the first capacitor and to a ground terminal, and a second transistor coupled to the second capacitor and to a ground terminal
Data Source
AI summary
A device includes a first bit cell, a second bit cell, and a multiply and average (MAV) circuit. The MAV circuit includes a first selection circuit and a second selection circuit. The first selection circuit has a first selection input and coupled to first and second capacitor terminals, and the first selection circuit is configured to, responsive to a state of the first selection input, set respective states of the first and second capacitor terminals based on a state of the first bit cell. The second selection circuit has a second selection input and is coupled to the first and second capacitor terminals. The second selection circuit is configured to, responsive to a state of the second selection input, set the respective states of the first and second capacitor terminals based on a state of the second bit cell.