Computation Using Non-Contact Making Devices TRIZ Cases
- Configurable Hybrid Adder Circuitry for Programmable Logic
Configurable hybrid adder circuitry reduces addition delay time by combining ripple carry and carry select blocks via carry look-ahead architecture.
- Neural Network Adder Multiplexer Controller for Reduction Overhead
A neural network adder and multiplexer controller manages data flow using reset and phase signals to separate processing logic.
- Array Processor Parallel Paths Opcode Control
General purpose array processor executes matrix operations via parallel processing paths and opcode control elements.
- Neural Circuit Emulating Biological Behaviors
Time multiplexed neuron and synapse circuits emulate biological neural behaviors, reducing hardware complexity for real-time low-power computations.
- Variable-Size Signed Operand Multiplier Circuit
A multiplier circuit generates single bit products using logical AND functions and selectively inverts specific bits to handle variable operand sizes.
- Analysis Mesh Data Generation for Complex CAD Shapes
A control device retrieves model mesh data to generate analysis meshes from complex CAD geometry without manual shape division.
- Sparsity-Aware CiM MAC Hardware for High-Precision AI Acceleration
A sparsity-aware compute-in-memory core restricts serial bit selection to non-zero values during multiply and accumulate operations.
- Reconfigurable SIMD Units Exchange Intermediate Results
Reconfigurable SIMD units exchange intermediate results to compute combined high precision complex arithmetic operations.
- Hybrid Arithmetic Logic Unit Segmented Adder Design
Segmented adder stages eliminate dead execution cycles by producing usable partial results each cycle, maintaining single-operation throughput.
- Neural Network Weight Quantization via Hypersurface Constraints
Segmenting neural network weights into sub-vectors constrained near a hypersphere enables precise quantization with minimal computational overhead.
- Sparse Weight Tensor MAC Operations for AI Chip Efficiency
Sparse weight tensors reduce data points in multiply-accumulate operations, lowering power consumption and design footprint without adding hardware units.
- Macrocell Adder with Bypass Carry Path for Crypto Processors
A macrocell adder block routes carry signals through a bypass path to optimize silicon area and processing speed.
- 6T Bit Cell Compute-in-Memory for CNN Power Reduction
A 6-transistor bit cell array performs multiply-and-average operations directly within memory storage nodes.
- Neural Network Accelerator Precision Scaling
A neural network accelerator uses bit operators and shifters to process feature data with varying precision levels.
- PIM Device MAC Operator Testing via Test Mode Signal
A PIM device integrates a MAC operator with distinct multiplying and adding blocks to perform arithmetic directly within memory.
- Configurable Three-Input ALU for Viterbi and Turbo Decoder Hardware Reuse
A configurable three-input arithmetic logic unit merges decoding functions via MINST instructions.
- Arithmetic Circuit Parallel Rounding Preprocessor
Arithmetic circuit employs parallel rounding preprocessor and postprocessor modules to reduce bit width in register storage.
- Integer Division via Floating-Point Reciprocal Pipelining
Leverages floating-point reciprocal hardware to perform pipelined integer division, resolving performance bottlenecks on conventional processors.
- Floating Point Multiplier Sticky Bit Determination Logic
Parallel sticky bit detection reduces processing time by computing values before final product generation, avoiding serial delays.
- Dual-Output Logic Entity for Fast Carry Propagation in Adders
A dual-output logic entity generates sum and carry values simultaneously using lookup tables and multiplexers.