Neural Network Accelerator Precision Scaling
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Solution Overview
Problem
Existing precision scalable neural network accelerators face challenges in reducing hardware area and power consumption while maintaining accuracy, as they require varying data precision based on application-specific accuracy needs.
Innovation Solution
The proposed neural network accelerator includes bit operators, adders, shifters, and accumulators that process input feature data and weight data with varying bit lengths, allowing for precision scalable operations. The shift values are determined based on the number of digits of the feature bits and weight bits, enabling efficient computation with reduced hardware area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the precision of data is reduced to decrease memory usage and computation, then memory usage and computation are reduced, but the accuracy of neural network computation is reduced
Solution Approach 1:
The patent implements dynamic precision scaling by allowing the neural network accelerator to adaptively adjust the number of bits used for data representation based on the specific computational requirements of different neural network layers and operations. This enables the system to use lower precision (fewer bits) where high accuracy is not critical, while maintaining higher precision where needed, thus resolving the contradiction between reducing memory/computation and maintaining accuracy.
2Adaptability or versatility
If a precision scalable neural network accelerator is implemented to support various applications with different accuracy requirements, then adaptability is improved, but hardware area and power consumption are increased
Solution Approach 1:
The patent designs a universal neural network accelerator architecture that can handle multiple precision requirements using the same hardware resources. The bit operators, adders, shifters, and accumulators are designed to be precision-agnostic, capable of processing data at different bit widths without requiring separate dedicated hardware for each precision level. This multi-functionality allows the system to support various applications with different accuracy needs while avoiding the hardware area increase that would result from implementing separate accelerators for each precision level.
3Adaptability or versatility
If a precision scalable neural network accelerator is implemented to support various applications with different accuracy requirements, then adaptability is improved, but power consumption is increased
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting the precision parameter (number of bits) based on the computational requirements of different neural network operations. The system can change the bit width parameter for feature data and weight data depending on the specific application and layer requirements, allowing it to optimize power consumption by using lower precision (fewer bits) when high accuracy is not necessary, while still maintaining the capability to use higher precision when needed.
Data Source
AI summary
Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature 5 bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number 10 of digits of the addition result depending on a shift value to generate a shifted addition result and an accumulator generating output feature data based on the shifted addition result.