Floating Point Multiplier Sticky Bit Determination Logic
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Solution Overview
Problem
Existing floating-point multiplication techniques require serial processing to determine the sticky bit value, which delays rounding evaluation until the final product is produced, and existing solutions either add complexity or require significant hardware.
Innovation Solution
A data processing apparatus that uses half-adder structures and combination logic to determine the sticky bit value from 2n-bit vectors before the final sum operation, allowing parallel processing and reducing hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If serial processing is used to determine the sticky bit value after final product production, then hardware complexity is reduced, but processing time increases
Solution Approach 1:
The patent applies preliminary action by computing the sticky bit value in parallel with the final product generation using half-adder structures and combination logic, rather than waiting for the final product to be produced. This allows the sticky bit determination to be performed in advance, eliminating the serial dependency and reducing overall processing time while maintaining reasonable hardware complexity through efficient logic design.
2Loss of time
If parallel processing is used to determine the sticky bit value before final sum operation, then processing time is reduced, but hardware complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the 2n-bit vectors into segments for parallel processing. Specifically, it uses half-adder structures that process portions of the bits independently, and combination logic that merges these partial results. This segmentation enables parallel computation of the sticky bit value without requiring a complete parallel implementation of the entire multiplication process, thus achieving time reduction with controlled hardware complexity increase.
Solution Approach 2:
The patent uses combination logic as an intermediary element that bridges the parallel half-adder structures and the final sum operation. This intermediary component efficiently integrates the parallelly computed partial sticky bit values, allowing the system to benefit from parallel processing speedups while managing hardware complexity through a structured intermediate processing stage rather than direct full parallelism.
3Reliability
If existing solutions for sticky bit determination are implemented, then rounding evaluation can proceed, but hardware requirements increase significantly
Solution Approach 1:
The patent applies self-service by designing the half-adder structures and combination logic to automatically determine the sticky bit value as an inherent byproduct of the multiplication process, rather than requiring separate dedicated hardware for sticky bit computation. The existing computational resources are utilized to simultaneously produce both the final product and the sticky bit value, achieving reliable rounding evaluation without significant additional hardware requirements.
Data Source
AI summary
A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises multiplier logic for multiplying the first and second n-bit significands to produce a pair of 2n-bit vectors, and sum logic operable to perform a sum operation to add a first set of bits of each of the pair of 2n-bits vectors. Sticky determination logic is also provided for determining from a second set of bits of each of the pair of 2n-bit vectors a sticky value, and selector logic is then used to derive the n-bit result from the output of the sum logic with reference to the sticky value. The sticky determination logic comprises a half-adder structure operable to generate carry and sum vectors from a negated version of the second set of bits of each the pair of 2n-bit vectors, and combination logic for performing a logical XOR operation on the carry and sum vectors with the least significant carry bit set to a logic one value. The sticky value can then be derived from the output of the combination logic. This provides a particularly efficient technique for determining the sticky value without awaiting the production of the final product in non-redundant form.