PIM Device MAC Operator Testing via Test Mode Signal
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Solution Overview
Problem
The increasing complexity of neural networks for artificial intelligence applications leads to exponential computation requirements, which are hindered by the limitations of data communication between separate processor and memory systems, necessitating an integrated processor-memory device for improved performance.
Innovation Solution
A Processing-in-Memory (PIM) device with a built-in multiplication/accumulation (MAC) operator, comprising a multiplying block and an adding block, that performs arithmetic operations directly within the memory device, and a test mode signal to facilitate testing of the MAC operator's functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a general hardware system with separate memory and processor is used, then the system structure is simple and easy to manufacture, but the data communication limitation between memory and processor degrades artificial intelligence performance
Solution Approach 1:
The patent merges the processor and memory into a single integrated device, combining the computing unit with multiple memory banks within the same hardware package. This integration eliminates the need for external data communication between separate processor and memory systems, directly resolving the bottleneck that degraded AI performance while maintaining a manageable system structure through modular design
2Productivity
If the number of layers in neural network is increased to improve AI performance, then the computation requirement increases exponentially, but the separate processor-memory system cannot handle the increased computation efficiently
Solution Approach 1:
By integrating the computing unit directly within the memory device, the system enables in-memory computing that performs arithmetic operations on data while it is stored. This eliminates the energy-intensive data movement between separate processor and memory, allowing the system to handle exponentially increasing computation requirements from deeper neural networks without proportional increases in power consumption
3Speed
If a PIM device with integrated processor and memory is used, then the data processing speed is improved, but the device complexity increases
Solution Approach 1:
The computing unit is integrated directly within the memory device structure, combining storage and processing functions in a single location. This integration enables data to be processed immediately upon retrieval without external communication overhead, significantly improving data processing speed while the modular architecture keeps the increased complexity contained within the device rather than the system level
4Reliability
If testing is performed on the MAC operator in the PIM device, then the functionality can be verified, but the testing complexity increases due to the integrated structure
Solution Approach 1:
The patent extracts the MAC operator as a distinct, independently testable functional unit within the integrated PIM device. By defining the MAC operator as a separate module with its own input terminals and output terminals, the design enables targeted testing of the arithmetic functionality without requiring testing of the entire integrated device, thereby verifying reliability while managing testing complexity through modular functional decomposition
Data Source
AI summary
A processing-in-memory (PIM) device includes a multiplication/accumulation (MAC) operator. The MAC operator includes a multiplying block and an adding block. The multiplying block includes a first multiplier and a second multiplier. The first multiplier performs a first multiplying calculation of first half data of first data and first half data of second data. The second multiplier performs a second multiplying calculation of second half data of the first data and second half data of the second data. The adding block performs an adding calculation of first multiplication result data outputted from the first multiplier and second multiplication result data outputted from the second multiplier. The MAC operator receives a test mode signal having a first level to perform a test operation for the multiplying block.