Array Processor Parallel Paths Opcode Control
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Solution Overview
Problem
Traditional communication systems face resource constraints in designing specialized circuitry to perform a wide range of matrix-related operations, leading to strain on budget, space, and power usage due to their complexity and legacy support of older IEEE standards.
Innovation Solution
A general purpose array processor is configured with multiplexers, multipliers, arithmetic logic units (ALUs), and an opcode control element to perform various matrix operations, allowing for parallel processing paths that can execute multiple operations efficiently, including real and complex matrix multiplications, thereby reducing the need for specialized circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If specialized circuitry is designed to perform various matrix-related algorithms, then processing capability is improved, but device complexity and resource usage (budget, space, power) increase
Solution Approach 1:
The patent implements a universal array processor that can perform multiple matrix-related algorithms (FFT, spatial processing, MMSE, channel determination, weight computation, phase correction) using a single reconfigurable hardware platform. The processor uses programmable multipliers, ALUs, and multiplexers controlled by opcodes to execute different algorithms, eliminating the need for separate specialized circuitry for each function.
Solution Approach 2:
The array processor employs dynamic reconfiguration through opcode control to change its functionality on-the-fly. The processor can switch between different matrix operations and algorithms by loading different opcode sequences, allowing the same hardware to adapt to different processing requirements without physical reconfiguration.
2Adaptability or versatility
If more specialized circuitry is added to support legacy IEEE standards, then compatibility is improved, but resource strain (budget, space, power) worsens
Solution Approach 1:
The universal array processor can implement legacy IEEE standards through software-based algorithms executed on the reconfigurable hardware. Instead of adding dedicated circuitry for each legacy standard, the processor uses programmable multipliers and ALUs to perform the required matrix operations, reducing hardware overhead and power consumption while maintaining compatibility.
3Productivity
If parallel processing paths are implemented, then processing throughput is improved, but device complexity increases
Solution Approach 1:
The array processor is divided into multiple independent processing elements including multipliers, ALUs, and multiplexers that can operate in parallel. Each processing element handles a portion of the matrix operation, and results are combined through the multiplexer network, enabling throughput improvement through modular parallelism.
Solution Approach 2:
The patent combines multiple processing paths into a unified array processor architecture where results from parallel operations are merged through multiplexers. This allows the system to achieve high throughput by combining simpler processing units rather than using a single complex processor.
Data Source
AI summary
General purpose array processing techniques including processing methods and apparatus. Processors may include parallel processing paths designed with reusable computational components such as multipliers, multiplexers, and ALUs. Flow of data through the paths and operations performed may be controlled based on opcodes. Processors may be shared, scalable, and configured to perform matrix operations. In particular, such operation may be useful for physical sections of MIMO-OFDM communication systems.