Integer Division via Floating-Point Reciprocal Pipelining
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Solution Overview
Problem
Conventional computer systems lack efficient hardware resources for performing integer division operations, relying on software implementations that are not optimized for performance on conventional processors like CPUs and GPUs, especially when the bit-width of the floating-point mantissa is insufficient for the integer bit-width.
Innovation Solution
A method for performing integer division using a set of steps involving partial quotients and remainders, leveraging single-precision floating-point hardware by computing and adjusting partial quotients and remainders through floating-point reciprocal operations, enabling efficient execution on conventional processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based integer division is implemented using classical shift-and-subtract algorithm, then it can be executed on conventional processors without dedicated hardware, but the execution performance is poor as it computes no more than one result bit per step
Solution Approach 1:
The patent replaces the mechanical iterative shift-and-subtract algorithm with a mathematical approach using floating-point reciprocal operations. By computing the reciprocal of the divisor and multiplying it with the dividend, the method achieves parallel computation of multiple quotient bits simultaneously, dramatically improving performance while maintaining compatibility with conventional CPU and GPU hardware that supports floating-point operations.
Solution Approach 2:
The patent changes the computational parameters by using floating-point reciprocal operations instead of integer arithmetic. This allows leveraging the higher performance of floating-point units in conventional processors, transforming the division operation into a sequence of multiplication and adjustment steps that execute faster on standard hardware.
2Productivity
If floating-point reciprocal operation is used to implement integer division, then execution performance improves, but it requires floating-point mantissa bit-width to be larger than integer bit-width, which is not satisfied by standard single-precision floating-point (24-bit mantissa vs 32-bit integer)
Solution Approach 1:
The patent segments the 32-bit integer division into multiple stages, each handling a portion of the computation. By dividing the problem into manageable parts and processing them sequentially with adjustments, the method achieves accurate 32-bit integer division results using only 24-bit floating-point mantissa precision, overcoming the precision limitation of standard single-precision floating-point hardware.
Solution Approach 2:
The patent uses partial quotient computation where each floating-point reciprocal operation computes an approximate quotient that is then refined through adjustment steps. This partial action approach allows achieving full precision results through multiple less-precise intermediate computations, effectively working around the 24-bit mantissa limitation.
3Productivity
If specialty arithmetic operations like floating-point fused-multiply-add (FMA) are used, then integer division performance improves, but these operations are not supported by dedicated hardware resources on conventional CPUs and GPUs
Solution Approach 1:
The patent designs a method that uses universal floating-point multiplication and addition operations that are supported by all conventional CPUs and GPUs. By avoiding specialty operations like FMA and using only standard floating-point instructions, the method achieves high performance integer division on diverse hardware platforms, demonstrating universal compatibility across conventional processors.
Data Source
AI summary
One embodiment of the present invention sets forth a technique for performing fast integer division using commonly available arithmetic operations. The technique may be implemented in a two-stage process using a single-precision floating point reciprocal in conjunction with integer addition and multiplication. Furthermore, the technique may be fully pipelined on many conventional processors for performance that is comparable to the best available high-performance alternatives.