Dual-Output Logic Entity for Fast Carry Propagation in Adders
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Solution Overview
Problem
Conventional ripple carry adders are limited by the speed of carry signal propagation, which constrains the performance of arithmetic operations, and existing faster carry propagation methods, such as look-ahead carry logic, require higher component density.
Innovation Solution
A logic entity with two outputs is implemented using lookup tables and multiplexers to simultaneously generate carry and sum values, allowing for efficient adder and macro implementations with minimal hardware overhead, enabling faster carry propagation without increasing component density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional ripple carry adder is used, then component density is low, but carry propagation speed is slow
Solution Approach 1:
The patent pre-calculates and stores sum and carry values for both carry-in=0 and carry-in=1 conditions in lookup tables before the actual addition operation. This preliminary action allows the carry signal to be propagated instantly by simply selecting the pre-computed result, eliminating the sequential propagation delay inherent in conventional ripple carry adders while maintaining simple logic circuitry.
2Speed
If look-ahead carry logic is used, then carry propagation speed is fast, but component density increases
Solution Approach 1:
The patent merges the functions of sum generation and carry generation into a single lookup table structure that produces both outputs simultaneously. By combining these functions and using the input signals and their complements directly, the design achieves fast carry propagation without requiring the additional logic gates and components that traditional look-ahead carry circuits demand.
Solution Approach 2:
The patent creates complementary versions of input signals (A and B) and their sums, storing results for both carry-in=0 and carry-in=1 conditions. This copying approach allows instant carry propagation by selecting between pre-computed complementary results, achieving fast speed without increasing component density since the same lookup table resources serve dual purposes.
3Productivity
If conventional ripple carry adder is used, then hardware requirements are minimal, but arithmetic operation speed is slow
Solution Approach 1:
The patent pre-calculates sum and carry values for all possible input combinations and both carry-in conditions, storing them in lookup tables before the actual addition operation occurs. This preliminary computation eliminates the sequential carry propagation time during actual arithmetic operations, significantly improving productivity while maintaining minimal hardware requirements through efficient lookup table utilization.
Data Source
AI summary
An improved logic entity with two outputs for efficient adder and other macro implementations providing fast response with reduced area requirements, comprising a first lookup table for generating a first output for the carry out value for a carry-in of zero and a second output for the sum value for a carry-in of one; a second lookup table for generating a first output for the carry out value for a carry-in of one and a second output for the sum value for a carry-in of zero; a first multiplexer is connected to a first input from the first output of the first lookup table and a second input from the first output of the second lookup table; a second multiplexer is connected to a first input from the second output of the first lookup table and a second input from the second output of the second lookup table; thereby, getting two output taps for sum and carry implementation.