Variable-Size Signed Operand Multiplier Circuit
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Solution Overview
Problem
Existing digital signal processors (DSP) face inefficiencies in multiplying and accumulating digital operands of varying lengths, leading to increased complexity and power consumption due to the need for hardwired circuitry and modified adder cells, which are not suitable for operands of different sizes.
Innovation Solution
A method and apparatus for multiplying signed operands of different bit lengths by generating single bit products using a logical AND function, selectively inverting specific products, and adding '1' bit values at specific positions to produce a final product, allowing for efficient multiplication and accumulation of operands with varying sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hardwired circuitry and modified adder cells are used to multiply and accumulate digital operands, then multiplication and accumulation can be performed, but hardware complexity and power consumption increase when operands have different sizes
Solution Approach 1:
The patent uses dynamic control signals to selectively activate or deactivate specific circuit components based on the sizes of the input operands. The control logic dynamically configures the multiplier to handle different operand size combinations (e.g., 8x16, 16x32, 32x64 bits) without requiring separate hardwired circuits for each size combination, thereby reducing overall hardware complexity while maintaining adaptability.
Solution Approach 2:
The patent designs a universal multiplier architecture that can perform multiplication and accumulation operations on operands of various sizes using the same core circuitry. The universal adder cells and control logic can adapt to different operand configurations, eliminating the need for multiple specialized circuits and reducing hardware complexity.
2Adaptability or versatility
If hardwired circuitry and modified adder cells are used to multiply and accumulate digital operands, then multiplication and accumulation can be performed, but power consumption increases when operands have different sizes
Solution Approach 1:
The patent employs dynamic control signals that enable the multiplier to selectively activate only the necessary circuit components based on the actual operand sizes being processed. This dynamic configuration prevents unnecessary switching activity and power consumption in circuit sections that are not needed for the current operation, thereby reducing overall power consumption while maintaining the ability to handle various operand size combinations.
3Measurement precision
If standard multiplication methods are used for signed operands of different bit lengths, then correct results can be obtained, but processing speed decreases due to additional inversion and addition steps
Solution Approach 1:
The patent performs preliminary detection of the sign bits of the input operands and pre-configures the control logic accordingly. Based on the sign detection, the controller pre-determines which inversion operations are needed and configures the circuit in advance, avoiding sequential sign checking and conditional branching during the multiplication process, thereby improving processing speed while maintaining accuracy for signed operands of different bit lengths.
Data Source
AI summary
Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na−1 multiplied with the second operand bits 0 to nb−2, selectively inverting the single bit products of the signed second operand bits 0 to na−2 multiplied with the signed second operand bit nb−1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb−1, na−1 and na+nb−1 for receiving a final product.