Arithmetic Circuit Parallel Rounding Preprocessor
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Solution Overview
Problem
Existing arithmetic circuits that perform multiplication and rounding processes together experience increased processing delay due to combined arithmetic and rounding operations, which affects their performance.
Innovation Solution
The proposed arithmetic circuit includes a rounding preprocessor and postprocessor that operate in parallel with the arithmetic unit, reducing the number of bits processed and allowing for pipelined operation, thereby reducing processing delay and circuit scale while maintaining high-speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the arithmetic circuit performs both arithmetic processing and rounding process together, then the circuit can complete both operations, but the processing delay increases
Solution Approach 1:
The rounding process is divided into two independent modules: a rounding preprocessor that operates in parallel with the arithmetic unit, and a rounding postprocessor that operates sequentially. This segmentation allows the time-consuming rounding operations to be distributed and partially parallelized, reducing the overall critical path delay while maintaining complete functionality.
Solution Approach 2:
The rounding preprocessor performs preliminary rounding calculations in parallel with the arithmetic unit during the arithmetic processing stage. By preparing rounding values beforehand using the lower bits of the multiplication result, the circuit avoids adding rounding delay to the critical path, thus reducing total processing delay while maintaining accuracy.
2Adaptability or versatility
If the arithmetic circuit performs arithmetic and rounding together, then both functions are integrated, but the circuit scale increases
Solution Approach 1:
The circuit is segmented into distinct functional blocks: arithmetic unit, rounding preprocessor, register, and rounding postprocessor. Each block has a dedicated function with optimized bit-width, allowing independent sizing and optimization. This modular segmentation reduces overall circuit complexity compared to a monolithic design while preserving full functionality.
Solution Approach 2:
Different parts of the circuit process different numbers of bits based on their specific functions. The rounding preprocessor works with (m-k) bits, the register stores (n+k+1) bits, and the postprocessor handles (k+1) bits. This local optimization of bit-width in each segment reduces the total circuit scale while maintaining the ability to perform both arithmetic and rounding operations.
Data Source
AI summary
According to one embodiment, an arithmetic circuit includes follows. The arithmetic unit performs an arithmetic operation including addition and multiplication to generate a first value of (n+m) bits. The rounding preprocessor performs an OR operation on lower (m−k) bits of the first value to generate a second value of 1 bit. The register stores a third value of (n+k+1) bits obtained by concatenating upper (n+k) bits of the first value and the second value. The rounding postprocessor calculates a carry bit value of 1 bit from a most significant bit of the third value and lower (k+1) bits of the third value, and adds the carry bit value to upper n bits of the third value.