6T SRAM Cell Separate Supply Voltage Read Stability
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Solution Overview
Problem
Conventional 6T static random access memory cells suffer from read disturb and write failure issues due to voltage instability and interference between nodes during reading and writing operations, leading to data flipping and unsuccessful data storage.
Innovation Solution
The proposed 6T static random access memory cell design includes a first and second inverter with NMOS transistors, where the first word line provides ON signals to turn on the first NMOS transistor, and a second high supply voltage provides a boost voltage, allowing for separate timing of word lines during writing and reading to prevent interference and reduce voltage requirements, thereby stabilizing data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional 6T SRAM cell uses single supply voltage for both nodes, then device complexity is reduced, but voltage instability and node interference occur during read/write operations
Solution Approach 1:
The patent divides the single supply voltage into two separate high supply voltages (first high supply voltage for first node, second high supply voltage for second node). This segmentation allows independent voltage control for each node, preventing voltage instability and node interference during read/write operations while maintaining reliable data storage.
2Ease of operation
If conventional 6T SRAM cell uses simultaneous word line activation, then writing operation is simplified, but read disturb and write failure issues occur due to voltage division
Solution Approach 1:
The patent employs periodic or phased activation of word lines instead of simultaneous activation. By controlling the timing of word line signals, the circuit performs write and read operations in distinct phases, preventing voltage division and node interference that cause read disturb and write failure, thereby improving data storage reliability.
3Use of energy by moving object
If conventional 6T SRAM cell uses standard voltage levels, then power consumption is moderate, but higher voltage is required for reliable data writing and reading
Solution Approach 1:
The patent changes the voltage parameter by introducing separate high supply voltages for different nodes instead of using standard uniform voltage levels. This parameter change enables reliable data writing and reading at lower overall power consumption by optimizing voltage distribution across the circuit, preventing voltage instability without requiring uniformly high voltage throughout.
Data Source
AI summary
A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first NMOS transistor, and a second NMOS transistor. A first high supply voltage and a low supply voltage are coupled to the first inverter. A second high supply voltage and the low supply voltage are coupled to the second inverter. The first NMOS transistor has a gate terminal coupled to a first word line. The first NMOS transistor has a source terminal coupled to the first node. The second NMOS transistor has a gate terminal coupled to a second word line, and the second NMOS transistor has a source terminal coupled to the second node. The first word line provides ON signals to turn on the first NMOS transistor, and the second high supply voltage provides a first boost voltage simultaneously.