8T SRAM With Segmented Write Word Lines
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Solution Overview
Problem
Current 8T and 10T subthreshold SRAMs suffer from write disturbs due to shared word lines and low read operation speed, which affect the stability and performance of static random access memories used in high-speed computing applications.
Innovation Solution
The proposed solution involves a 8T SRAM architecture with separated write word lines for selected and unselected memory cells, along with a feedback circuit to enhance read operation speed by discharging the read bit line, thereby reducing write noise and improving static noise margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shared word lines are used in 8T and 10T subthreshold SRAMs, then device complexity is reduced, but write disturbs occur affecting stability
Solution Approach 1:
The patent divides the word line structure into separate write word lines (WWL0, WWL1) for different memory cells, allowing independent control of write operations. This segmentation prevents write disturbs to unselected cells while maintaining manageable device complexity through systematic organization of the separated lines.
2Reliability
If additional transistors are added to improve read stability, then read stability improves, but device complexity increases
Solution Approach 1:
The patent enhances read stability locally at the sense amplifier stage rather than increasing transistor count throughout the entire memory cell. The sense amplifier is specifically optimized with additional transistors (N3, N4, P3, P4) to improve read stability, while the memory cell structure itself maintains the efficient 8T configuration.
3Speed
If feedback circuit is added to discharge read bit line, then read operation speed increases, but device complexity increases
Solution Approach 1:
The feedback circuit proactively discharges the read bit line before the read operation completes, preparing the circuit for the next operation in advance. This preliminary action reduces the overall read operation time by overlapping the discharge process with the sense amplifier operation, thereby increasing read speed without proportionally increasing complexity.
4Object-generated harmful factors
If separated write word lines are used, then write noise is reduced, but device complexity increases
Solution Approach 1:
The patent segments the write word line control into separate lines (WWL0, WWL1) that can be independently activated. This segmentation isolates write noise to only the selected memory cell's word line, preventing noise propagation to other cells. The systematic routing and control logic manage the increased complexity through organized design.
Data Source
AI summary
A memory device is disclosed. The memory device includes a memory array including a first memory cell arranged in a first row and a first column and a second memory cell arranged in the first row and a second column next to the first column. The first memory cell is configured to perform a write operation in response to a first write signal transmitted through a first write word line. The second memory cell is configured to perform the write operation in response to a second write signal transmitted through a second write word line. The second write word line is separated from and next to the first write word line. The first write signal and the second write signal have different logic values.