Digital Storage TRIZ Cases

A pre-charge circuit charges bit lines to a sub-VDD voltage level using pulsed signals.

A memory device generates global and local write signals using main and local I/O circuits to manage data writing operations.

A memory controller applies time-varying retention voltages to storage elements based on detected error information.

Pre-charge capacitors balance discharge speeds to widen the sensing margin, resolving reliability issues from high read currents.

Segmented write word lines prevent write disturbs while a feedback circuit discharges the read bit line to boost operation speed.

Segmented shield lines block electromagnetic cross-coupling between adjacent digit lines, enabling faster concurrent access without data corruption.

Arbitration circuitry manages shared ZQ calibration resistors across multiple memory channels in package on package devices.

A programmable data storage component with ferroelectric capacitors restores polarization states during power cycles.

Relocating the row data buffer array adjacent to the DQ pad shortens read/write paths, resolving speed and area trade-offs.

A reference voltage generator mirrors multiplexer current leakage to adjust the output, resolving logic level mischaracterization in sense amplifiers.

A pre-driver adjusts data transferrer voltage levels before main driver activation to accelerate signal propagation in semiconductor memory devices.

Dynamic sampling window adjustment detects falling edge position shifts caused by voltage fluctuations, preventing erroneous data reads in DDR SDRAM.

Replica path and follower devices regulate MTJ voltages to minimize leakage currents under process variations.

A 4T4R ternary weight cell uses cross-coupled magneto tunnel junctions and field effect transistors to generate logical values.

A memory device with configurable segments enables flexible data access granularity across multiple operational modes.

A memory array stores data in a preferred bias condition to reduce soft error rates.

A variable resistance memory read circuit uses dual switch layers to modulate electrical conductivity for multilevel data storage.

External magnetic fields identify abnormal MRAM cells via coercivity, reducing testing time and cost.

A dynamic output enable signal generation circuit adjusts count values to synchronize with external clock signals.

A semiconductor chip design extends memory cells toward edges to create a cross shape that positions pads centrally.

Segmenting the internal memory allows the host buffer region to store backup data, reducing manufacturing costs while maintaining operating performance.

Hardware comparison circuit processes data sets via DMA to reduce CPU load and improve processing speed.

Single recovery pulses correct drift and erroneous levels, eliminating DRAM-like refresh penalties.

A combinational resistive change element array stores multiple bits using relational resistance states to boost memory density.

Feedback amplifier dynamically adjusts conductivity to maintain voltage across MTJ element, resolving sensitivity limits in high-density memory arrays.

Partitioned data bus eliminates rank-to-rank turnaround overhead to double peak bandwidth in stacked memory devices.

Address pads receive data masking signals to eliminate separate pads, reducing device complexity and current consumption.

A segmented internal voltage generator supplies stable core and peripheral voltages using dedicated reference sources.

A write assist circuit uses PMOS transistors to couple bit-lines to voltage rails during memory write cycles.

A voltage generator uses a level compensator to boost peripheral circuit voltage during column path commands.

Initialization signal generation circuit uses a counter unit to delay the counting initialization signal based on refresh timing.

A recalibration module detects delayed strobe signal proximity to reference edges and triggers independent delay adjustments.

High voltage transistors with thicker gate dielectrics accelerate bit line precharging, overcoming conductivity limits from reduced power supply voltages.

A storage array circuit separates computational dual port SRAM cells from high-density memory to optimize data retention and logic processing.

A memory device controls row switches to weakly turn on selected word lines during bit line precharge periods.

Dual-polarity voltage pulses distinguish logic states in scaled memory devices, resolving overlapping threshold distributions that cause high error rates.

A magnetic random access memory section converts between read-write and read-only modes using control circuitry.

A memory device adjusts write pulse width based on detected temperature to maintain reliable data storage operations.

A two-bit memory device uses a chiral molecular spin filter to encode data in four resistance states.

Alternate gate coupling arrangement reduces memory cell unit area from 4.4 um2 to 3.3 um2 by removing the silicide blocking layer required for charge retention.

Input control circuit synchronizes chip selection signals with internal clock pulses to generate valid command and address data.

Group-level domain index controllers reduce buffer region size and power consumption by managing racetrack groups instead of individual tracks.

An ECC circuit corrects read codeword errors on a per symbol basis using adjacent memory cells.

Parallel hybrid switches merge tunnel and diffusion transistors to overcome the 60 mV/decade sub-threshold swing limit of standard MOS devices.

Extracting protocol logic from memory devices onto a separate integrated circuit resolves bus width constraints while maintaining communication compatibility.

Existing data lines act as sensors during pre-charge to detect light attacks without consuming extra memory space.