High Voltage Transistors for Fast Memory Bit Line Precharging
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Solution Overview
Problem
The challenge in memory technologies is to enhance sensing speed while dealing with reducing power supply voltages, which limit the magnitude of gate-to-source voltages and consequently the conductivity of transistors, hindering faster data processing.
Innovation Solution
The implementation of high voltage transistors with thicker gate dielectrics, allowing for higher dielectric breakdown voltages and greater threshold voltages, is used to precharge bit lines faster during memory reads, thereby increasing current drive and speeding up the sensing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If smaller transistor dimensions are used to achieve faster transistors, then transistor speed is improved, but breakdown voltage decreases
Solution Approach 1:
The patent changes the voltage parameter by introducing a boosted voltage signal (VBST) that temporarily exceeds the normal supply voltage (VDD). This voltage boosting mechanism allows the circuit to operate with higher voltages during critical periods (precharge and sensing phases) without permanently increasing the supply voltage, thus resolving the contradiction between speed and breakdown voltage constraints
Solution Approach 2:
The patent employs dynamic voltage control where the voltage applied to the bit line and control electrode varies over time. During precharge and sensing, high voltage is applied to maximize speed, while during normal operation, lower voltage is used to protect the transistor breakdown limits. This dynamic adjustment resolves the contradiction by adapting voltage levels to operational requirements
2Use of energy by moving object
If power supply voltage is reduced, then power consumption is lowered, but gate-to-source voltage magnitude decreases reducing conductivity
Solution Approach 1:
The patent applies preliminary action by precharging the bit line to a high voltage level before the actual read operation. This precharge phase prepares the circuit in advance with sufficient voltage headroom, ensuring that when the sensing operation begins, the transistors can operate at optimal conductivity levels despite the low overall supply voltage, thus maintaining reliability while keeping power consumption low
Solution Approach 2:
The patent uses periodic voltage boosting where high voltage is applied intermittently during specific phases (precharge and sensing) rather than continuously. This periodic high-voltage application ensures adequate conductivity during critical operations while maintaining low average power consumption, resolving the contradiction between power efficiency and conductivity requirements
3Reliability
If threshold voltage is lowered to increase gate-to-source voltage magnitude, then conductivity improves, but room for improvement decreases
Solution Approach 1:
The patent adds another dimension to voltage control by introducing a separate voltage boosting mechanism that operates independently of the threshold voltage. Instead of relying solely on lowering threshold voltage to increase gate-to-source voltage magnitude, the patent boosts the supply voltage itself during critical phases, providing additional headroom for improving conductivity without further reducing threshold voltage and thus preserving adaptability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster precharging and sensing by maintaining higher gate-to-source voltages, even at low threshold voltages, resulting in enhanced memory read speeds and improved conductivity, overcoming the limitations imposed by reduced power supply voltages.
Implementation Method 1
high voltage transistors with thicker gate dielectrics, allowing for higher dielectric breakdown voltages
Data Source
AI summary
A memory including a data line, a sense amplifier, and an array of memory cells. The memory includes a transistor for coupling the data line to memory cells of the array for reading. The transistor is biased at a voltage that is higher than a voltage that the data line is biased during precharging. The transistor is part of a regulation circuit. The regulation circuit includes transistors with a higher dielectric breakdown voltage than transistors of the sense amplifier.