4T4R Ternary Weight Cell With High On-Off Ratio
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Solution Overview
Problem
Current hardware accelerators for machine learning applications face challenges in efficiently performing matrix vector multiplications due to the power inefficiency and limitations of memory options like SRAM, RRAM, and STT-MRAM, which have low on/off ratios and high variation.
Innovation Solution
A ternary weight cell configuration using four magneto tunnel junctions (MTJs) and four N-type field effect transistors, with cross-coupling connections, allowing for logical values of {1, 0, −1} and achieving a high on/off ratio of output current, enabling efficient semi-digital matrix vector multiplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If nonvolatile memory options such as RRAM, FLASH or STT-MRAM are used, then the memory can store weights non-volitilely, but the on/off ratio is low and variation is high
Solution Approach 1:
The patent combines multiple memory elements (first and second resistive memory elements) with multiple transistors (first, second, third, and fourth transistors) into an integrated weight cell structure. This merging allows the system to achieve both non-volatile storage and high on/off ratio through the collective operation of the combined components, where the transistor network amplifies and stabilizes the memory element outputs.
Solution Approach 2:
The weight cell employs a composite structure integrating different types of components - resistive memory elements for non-volatile storage and field-effect transistors for signal control and amplification. This composite approach leverages the strengths of each component type: the memory elements provide non-volatility while the transistors provide high on/off ratio and low variation, achieving both requirements simultaneously.
2Speed
If SRAM is used for weight storage, then the memory is fast and volatile, but the area is large and power consumption is high
Solution Approach 1:
The patent replaces traditional volatile SRAM-based weight storage with a non-volatile resistive memory-based system. This substitution eliminates the need for continuous power supply to maintain weight values, dramatically reducing static power consumption while maintaining fast read speeds through the resistive memory's inherent speed advantages over SRAM in this specific application context.
Solution Approach 2:
The invention changes the fundamental operating parameters of the memory system by transitioning from volatile to non-volatile memory technology. This parameter change allows the system to maintain fast access speeds while reducing power consumption to near-zero during weight storage, as non-volatile memory elements retain their state without power.
3Productivity
If a memory element is introduced in each weight cell for matrix vector multiplication, then the computation can be performed in analog, but the device complexity increases
Solution Approach 1:
The weight cell design achieves multi-functionality by integrating multiple operations within a single cell structure. The first and second resistive memory elements can store different weight values, while the transistor network enables both read operations for analog computation and write operations for weight updates. This universal design allows the same structure to perform multiple functions, reducing overall system complexity despite the enhanced capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ternary weight cell configuration enhances the on/off ratio of output current, providing efficient and power-effective matrix vector multiplication, suitable for machine learning applications, while minimizing read disturb faults and allowing for complementary output on two lines.
Implementation Method 1
four magneto tunnel junctions (MTJs)
Implementation Method 2
four N-type field effect transistors
Data Source
AI summary
A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET being connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, a third FET and a third resistive memory element connected to a drain of the third FET, and a fourth FET and a fourth resistive memory element connected to a drain of the fourth FET, the drain of the third FET is connected to a gate of the fourth FET and the drain of the fourth FET being connected to a gate of the third FET.